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microcomputer mn102l00 mn102l2503/25a/25d/ 25z/25g/f25z/490a/62d/ 62f/62g lsi user's manual pub.no.22262-010e

request for your special attention and precautions in using the technical informa- tion and semiconductors described in this manual. (1) the approval of the japanese government is required for the export of any products and technologies listed in this manual which are subjected to the provisions of the foreign exchange and foreign trade law. (2) the contents of this manual are subject to change without notice to improve design, func- tion, or performance. (3) matsushita electronics assumes no responsibility or liability for damages or for infringe- ments of patents or other rights arising from use of the information in this manual. (4) the contents of this manual may not be copied or reproduced without permission in writ- ing from matsushita electronics. (5) this manual describes standard specifications. obtain the latest product standard specifi- cations before you design, purchase, or use. for inquiries regarding this manual or any matsushita semiconductor, please contact one of the sales offices listed at the end of this manual or the sales department of matsushita electronics corporation. panaxseries is a trademark of matsushita electric industrial co., ltd. the other corporation names, logotypes and product names written in this manual are trademarks or registered trademarks of their corresponding corporations. the mn102lf25z is manufactured and sold under the license agreement with bull cp8 inc., and the use of the mn102lf25z into the ic card is not allowed.
about this manual this manual is intended for assembly-language programming engineers. it describes the internal configuration and hardware functions of the MN102L25X series microcontrollers. warning please read and follow these instructions to prevent damage or reduced performance. text conventions this manual contains titles, sub-titles, special notes and warnings. supplementary comments appear in the sidebar. key information this note describes key points of an operation.
finding desired information this manual provides four methods for finding desired information quickly and easily. (1) an index for the front of the manual for finding each section. (2) a table of contents at the front of the manual for finding desired titles. (3) a list of figures at the front of the manual for finding illustrations and charts by names. (4) a chapter name is located at the upper corner of each page. related manuals mn10200 series linear addressing version lsi user manual (describes the mn10200 series specifications) mn10200 series linear addressing version instruction manual (describes the instruction set) mn10200 series linear addressing version c compiler user manual usage guide (describes the installation, commands, and options for the c complier) mn10200 series linear addressing version c compiler user manual language description (describes the syntax for the c complier) mn10200 series linear addressing version c compiler user manual library reference (describes the standard libraries for the c complier) mn10200 series linear addressing version cross assembler user manual lan- guage description (describes the assembler syntax and notation) mn10200 series linear addressing version c source code debugger user manual (describes the use of the c source code debugger) mn10200 series linear addressing version panaxseries installation manual (describes the installation of the c complier, cross-assembler, and c source code debugger and the procedures for using the in-circuit emulator) questions and comments please send your questions, comments and suggestions to the semiconductor design center closest to you. see the last page of this manual for a list of addresses and tele- phone numbers.

contents chapter 1 general description 0 1 2 3 4 5 6 7 8 9 chapter 2 bus interface chapter 3 interrupts chapter 4 timers chapter 5 serial interface chapter 6 analog interface chapter 7 atc chapter 8 ports chapter 9 appendix

contents 0 1 2 3 4 5 6 7 8 9 10 11
contents chapter 1 general description 1-1 general description .................................................................................... 2 1-1-1 introduction ............................................................................. 2 1-1-2 features ................................................................................. 2 1-1-3 overview ................................................................................ 5 1-2 basic specifications ................................................................................... 8 1-3 block diagram ............................................................................................ 10 1-4 pin description ........................................................................................... 12 1-4-1 list of pin functions ............................................................... 13 1-5 external dimensions ................................................................................... 23 chapter 2 bus interface 2-1 bus interface ............................................................................................... 26 2-1-1 overview ................................................................................ 26 2-1-2 control registers ................................................................... 32 2-1-3 rom burst mode timing ........................................................ 36 2-2 external memory connection examples ..................................................... 40 2-2-1 memory expansion mode (address/data separated mode) .. 40 2-2-2 external memory connection examples (address/data separated mode) ............................................ 42 2-2-3 memory expansion mode (address/data shared mode) ....... 48 2-2-4 external memory connection examples (address/data shared mode) ................................................. 50 chapter 3 interrupts 3-1 interrupts ..................................................................................................... 56 3-1-1 overview ................................................................................ 56 3-2 external interrupts ...................................................................................... 58 3-2-1 external pin interrupts ............................................................ 58 3-2-2 nmi interrupts ......................................................................... 58 3-3 interrupt setup examples ........................................................................... 60 3-3-1 external pin interrupt setup ................................................... 60 3-3-2 watchdog timer interrupt ....................................................... 62
chapter 4 timers 4-1 timers ......................................................................................................... 66 4-1-1 overview ................................................................................ 66 4-1-2 control registers .................................................................... 74 4-1-3 timer block diagrams ............................................................ 75 4-2 8-bit timer setup examples ....................................................................... 80 4-2-1 event counter using 8-bit timer ............................................ 80 4-2-2 clock output using 8-bit timer .............................................. 82 4-2-3 interval timer using 8-bit timer ............................................. 85 4-3 16-bit timer setup examples ..................................................................... 88 4-3-1 event counter using 16-bit timer .......................................... 88 4-3-2 pwm output using 16-bit timer ............................................. 90 4-3-3 two-phase pwm output using 16-bit timer .......................... 93 4-3-4 one-phase capture input using 16-bit timer ...................... 96 4-3-5 two-phase capture input using 16-bit timer ......................... 98 4-3-6 two-phase encoder input (4x) using 16-bit timer .................. 100 4-3-7 one-shot pulse output using 16-bit timer ............................ 102 4-3-8 external count direction control using 16-bit timer ............. 104 4-3-9 external reset control using 16-bit timer ............................. 106 chapter 5 serial interface 5-1 serial interface ............................................................................................ 110 5-1-1 overview ................................................................................. 110 5-1-2 control registers .................................................................... 111 5-1-3 serial interface connection .................................................... 113 5-2 serial interface setup examples ................................................................. 116 5-2-1 serial transmission in asynchronous mode using timer 2 ... 116 5-2-2 serial reception in synchronous mode using timer 2 .......... 120 5-2-3 serial transmission/reception in i 2 c mode using timer 3 .... 121 chapter 6 analog interface 6-1 analog interface .......................................................................................... 124 6-1-1 overview ................................................................................ 124 6-1-2 control registers .................................................................... 129 6-2 analog interface setup examples .............................................................. 130 6-2-1 one channel a/d conversion using an2 pin ........................ 130 6-2-2 multiple channel a/d conversion using an2 to an0 pins .... 132
6-1-2 control registers .................................................................... 129 6-2 analog interface setup examples .............................................................. 130 6-2-1 one channel a/d conversion using an2 pin ........................ 130 6-2-2 multiple channel a/d conversion using an2 to an0 pins .... 132 chapter 7 atc 7-1 atc ............................................................................................................ 136 7-1-1 overview ................................................................................ 136 7-1-2 control registers .................................................................... 138 7-2 atc setup examples ................................................................................. 139 7-2-1 serial reception ..................................................................... 139 chapter 8 ports 8-1 ports ........................................................................................................... 142 8-1-1 overview ................................................................................ 142 8-1-2 control registers .................................................................... 150 8-2 byte swap registers .................................................................................. 158 8-2-1 overview ................................................................................ 158 8-3 pullup control register ............................................................................... 159 8-3-1 overview ................................................................................ 159 chapter 9 appendix 9-1 electrical characteristics ............................................................................ 162 9-1-1 electrical characteristics 5 v ............................................................ 162 9-1-2 electrical characteristics 3 v ............................................................ 179 9-2 data appendix ............................................................................................ 205 9-2-1 list of special registers ......................................................... 205 9-2-2 address map .......................................................................... 262 9-2-3 list of pin functions ............................................................... 264 9-3 mn102l00 series linear address edition instructions .............................. 266 9-4 initialization program .................................................................................. 276 9-5 eprom version ......................................................................................... 278
9-5-1 overview ................................................................................ 278 9-5-2 connecting adaptor socket ................................................... 279 9-5-3 programming .......................................................................... 282 9-6 flash eeprom version ............................................................................. 292 9-6-1 overview ................................................................................ 292 9-6-2 flash eeprom programming ............................................... 293 9-6-3 prom writer mode ................................................................ 293 9-6-4 onboard serial programming mode ....................................... 294 9-6-5 hardware used in serial programming mode ........................ 294 9-6-6 connecting onboard serial programming mode .................... 296 9-6-7 system configuration for onboard serial programming ........ 297 9-6-8 onboard serial programming mode setup ............................ 299 9-6-9 branch to user program ......................................................... 301 9-6-10 serial interface for onboard serial programming ................. 302 9-6-11 prom writer/onboard serial programming .......................... 303
list of figures figure 1-1-1 address space ....................................................................... 5 figure 1-1-2 interrupt controller configuration ........................................... 7 figure 1-1-3 interrupt servicing sequence ................................................. 7 figure 1-3-1 block diagram ........................................................................ 10 figure 1-4-1 pin configuration .................................................................... 12 figure 1-4-2 osci, osco connection example ........................................ 22 figure 1-4-3 xi, xo connection example ................................................... 22 figure 1-4-4 reset pin connection example .............................................. 22 figure 1-4-5 wait signal control circuit connection example .................. 22 figure 1-5-1 external dimensions .............................................................. 23 figure 2-1-1 address space ....................................................................... 26 figure 2-1-2 bus controller ......................................................................... 27 figure 2-1-3 memory expansion mode (address/data shared pin configuration) .............................. 28 figure 2-1-4 memory expansion mode (address/data separated pin configuration) ......................... 28 figure 2-1-5 processor mode (address/data shared pin configuration) .............................. 29 figure 2-1-6 processor mode (address/data separated pin configuration) ......................... 29 figure 2-1-7 single-chip mode .................................................................... 30 figure 2-1-8 rom timing for burst mode (4 bytes for page size) ............. 36 figure 2-1-9 rom burst mode access timing ........................................... 37 figure 2-1-10 access timing memory connection example during rom burst mode ......................................................... 38 figure 2-2-1 memory connection example with 16-bit bus width (address/data separated mode) ............................................ 42 figure 2-2-2 memory connection example with 8-bit bus width (address/data separated mode) ............................................ 43 figure 2-2-3 no wait access timing with 16-bit bus width ....................... 44 figure 2-2-4 1 wait access timing with 16-bit bus width .......................... 44 figure 2-2-5 handshake access timing with 16-bit bus width .................. 45 figure 2-2-6 no wait access timing with 8-bit bus width ......................... 45 figure 2-2-7 1 wait access timing with 8-bit bus width ............................ 46 figure 2-2-8 handshake access timing with 8-bit bus width .................... 46
figure 2-2-9 access timing during bus request (address/data separated mode) ............................................ 47 figure 2-2-10 memory connection example with 16-bit bus width (address/data shared mode) ................................................. 50 figure 2-2-11 memory connection example with 8-bit bus width (address/data shared mode) ................................................. 51 figure 2-2-12 fixed wait access timing with 16-bit bus width ................... 52 figure 2-2-13 handshake access timing with 16-bit bus width .................. 52 figure 2-2-14 fixed wait access timing with 8-bit bus width ..................... 53 figure 2-2-15 handshake access timing with 8-bit bus width .................... 53 figure 2-2-16 access timing during bus request (address/data shared mode) ................................................ 54 figure 3-3-1 external pin interrupt timing .................................................. 61 figure 3-3-2 watchdog timer interrupt timing ........................................... 63 figure 4-1-1 event counter timing ............................................................. 68 figure 4-1-2 timer output, interval timer timing ....................................... 68 figure 4-1-3 pwm output timing (timer 6 and timer 7) ........................... 68 figure 4-1-4 pwm output timing (data write) (timer 6 and timer 7) ....... 69 figure 4-1-5 two-phase timer output timing (timer 6 and timer 7) ........ 69 figure 4-1-6 one-shot pulse output timing (timer 6 and timer 7) ........... 69 figure 4-1-7 one-phase capture input timing (timer 6 and timer 7) ....... 70 figure 4-1-8 two-phase capture input timing (timer 6 and timer 7) ....... 70 figure 4-1-9 two-phase encoder (4x) timing ............................................ 70 figure 4-1-10 two-phase encoder (1x) timing (timer 6 and timer 7) ....... 71 figure 4-1-11 external count direction control timing (timer 6 and timer 7) ............................................................. 71 figure 4-1-12 external count reset control (two-phase encoder) timing (timer 6 and timer 7) ............................................................. 71 figure 4-1-14 timer 0 block diagram ........................................................... 75 figure 4-1-15 timer 1 block diagram ........................................................... 75 figure 4-1-16 timer 2 block diagram ........................................................... 76 figure 4-1-17 timer 3 block diagram ........................................................... 76 figure 4-1-18 timer 4 block diagram ........................................................... 77 figure 4-1-19 timer 5 block diagram ........................................................... 77
figure 4-1-20 timer 6 block diagram ........................................................... 78 figure 4-1-21 timer 7 block diagram ........................................................... 78 figure 4-2-1 event counter timing ............................................................. 81 figure 4-2-2 clock output configuration (1) ............................................... 82 figure 4-2-3 clock output timing ............................................................... 84 figure 4-2-4 clock output configuration (2) ............................................... 85 figure 4-2-5 interval timer timing .............................................................. 87 figure 4-3-1 event counter timing ............................................................. 89 figure 4-3-2 pwm timing ........................................................................... 92 figure 4-3-3 pwm timing in double buffer mode ...................................... 92 figure 4-3-4 two-phase pwm timing ........................................................ 94 figure 4-3-5 two-phase pwm timing in double buffer mode ................... 95 figure 4-3-6 one-phase capture timing .................................................... 97 figure 4-3-7 two-phase capture timing .................................................... 99 figure 4-3-8 two-phase encoder input timing .......................................... 101 figure 4-3-9 one-shot pulse output timing ............................................... 103 figure 4-3-10 external count direction control timing ................................ 105 figure 4-3-11 external reset control timing ................................................ 107 figure 5-1-1 serial interface configuration ................................................. 110 figure 5-1-2 scnstr change timing ........................................................ 112 figure 5-1-3 asynchronous connection ...................................................... 113 figure 5-1-4 synchronous connection ....................................................... 113 figure 5-1-5 i 2 c mode connection ............................................................. 114 figure 5-2-1 asynchronous transmission configuration ............................ 116 figure 5-2-2 bit transmission timing in asynchronous mode .................... 118 figure 5-2-3 transmission/reception in i 2 c mode ..................................... 122 figure 6-1-1 analog interface configuration ............................................... 124 figure 6-1-2 a/d conversion timing ........................................................... 125 figure 6-1-3 one channel/single conversion timing ................................ 126 figure 6-1-4 multiple channels/single conversion timing ......................... 126 figure 6-1-5 one channel/continuous conversion timing ........................ 127 figure 6-1-6 multiple channels/continuous conversion timing ................. 127 figure 6-1-7 ananlog interface block diagram ........................................... 128 figure 6-2-1 one channel a/d conversion ................................................ 130
figure 6-2-2 multiple channel a/d conversion ........................................... 132 figure 6-2-3 a/d conversion timing ........................................................... 133 figure 7-1-1 atc operations ..................................................................... 137 figure 7-2-1 serial reception data transfer .............................................. 140 figure 7-2-2 last data transfer timing ...................................................... 140 figure 8-2-1 byte swap register ................................................................ 158 figure 9-1 system clock timing ............................................................. 197 figure 9-2 reset timing .......................................................................... 197 figure 9-3 data transfer signal timing (address/data separated mode, without wait) ............................................. 198 figure 9-4 data transfer signal timing (address/data separated, with wait) ............................................................ 199 figure 9-5 data transfer signal timing (address/data shared mode, without wait) .................................................. 200 figure 9-6 data transfer signal timing (address/data shared, with wait) ................................................................ 201 figure 9-7 data transfer signal timing (burst rom interface) .............. 202 figure 9-8 bus authority request signal timing ..................................... 203 figure 9-9 interrupt signal timing ........................................................... 203 figure 9-10 serial interface signal timing 1 (synchronous serial transmission: transfer in progress) ............................ 203 figure 9-11 serial interface signal timing 2 (synchronous serial transmission: transfer end timing at sbt input) ................. 203 figure 9-12 serial interface signal timing 3 (synchronous serial transmission: transfer end timing at sbt output) .............. 204 figure 9-13 serial interface signal timing 4 (synchronous serial reception) .............................................................................. 204 figure 9-14 timer/counter signal timing .................................................. 204 figure 9-5-1 memory map during eprom parallel mode .......................... 278 figure 9-5-2 pin configuration of adaptor socket ...................................... 279 figure 9-5-3 eprom pin configuration ...................................................... 280 figure 9-5-4 adaptor socket-mn102lp25x pin connection ....................... 281 figure 9-5-5 word program timing ............................................................ 285
figure 9-5-6 word program flow ............................................................... 286 figure 9-5-7 page program timing ............................................................. 289 figure 9-5-8 page program flow ............................................................... 290 figure 9-5-9 high-temperature test flow ................................................. 291 figure 9-6-1 memory map for flash eeprom version .............................. 292 figure 9-6-2 flash eeprom program flow ............................................... 293 figure 9-6-3 8-bit serial interface block diagram for serial writer ............. 294 figure 9-6-4 flash eeprom memory space ............................................. 295 figure 9-6-5 pin configuration during serial programming ....................... 296 figure 9-6-6 system configuration for onboard serial writer .................... 297 figure 9-6-7 target board-serial writer connection .................................. 297 figure 9-6-8 timing for onboard serial programming mode ...................... 299 figure 9-6-9 load program start flow ....................................................... 300 figure 9-6-10 reset service routine flow ................................................... 301 figure 9-6-11 interrupt service routine flow ............................................... 301 figure 9-6-12 data transfer timing .............................................................. 302 figure 9-6-13 programming flow ................................................................. 303
table 1-1-1 memory modes ....................................................................... 5 table 1-2-1 basic specifications ............................................................... 8 table 1-3-1 block functions ...................................................................... 11 table 1-4-1 list of pin functions ............................................................... 13 table 2-1-1 cs signal generation ............................................................. 27 table 2-1-2 list of bus interface control registers ................................... 32 table 3-1-1 list of interrupt control registers ........................................... 56 table 4-1-1 timer function ........................................................................ 66 table 4-1-2 list of timer control registers ............................................... 74 table 5-1-1 serial interface features ....................................................... 110 table 5-1-2 list of serial interface control registers ................................ 111 table 5-1-3 baud rate setup example in asynchronous mode (external oscillation at 20 mhz) ............................................. 115 table 5-1-4 baud rate setup example in asynchronous mode (external oscillation at 19.6608 mhz) .................................... 115 table 5-1-5 baud rate setup example in asynchronous mode (external oscillation at 17.2032 mhz) .................................... 115 table 5-1-6 baud rate setup example in asynchronous mode (external oscillation at 16 mhz) ............................................. 115 table 5-1-7 baud rate setup example in asynchronous mode (external oscillation at 14 mhz) ............................................. 115 table 5-1-8 baud rate setup example in asynchronous mode (external oscillation at 12 mhz) ............................................. 115 table 5-1-9 baud rate setup example in asynchronous mode (external oscillation at 10 mhz) ............................................. 115 table 5-1-10 baud rate setup example in asynchronous mode (external oscillation at 8 mhz) ............................................... 115 list of tables
table 6-1-1 a/d converter functions ........................................................ 125 table 6-1-2 list of a/d conversion control registers ............................... 129 table 7-1-1 atc functions ........................................................................ 136 table 7-1-2 list of atc control registers ................................................. 138 table 8-1-1 port functions ........................................................................ 142 table 8-1-2 list of port control registers .................................................. 150 table 8-1-2 pullup control registers ......................................................... 159 table 9-5-1 operating mode selection ...................................................... 282 table 9-6-1 clock frequency ..................................................................... 298
0 1 2 3 4 5 6 7 8 9 chapter 1 general description
2 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 1-1 general description 1-1-1 introduction the mn10200 series linear addressing version designs the new architecture for c-language programming based on a detailed analysis for embedded applications. this improves the system architecture in speed and function to meet the requirements in user systems including miniaturization and low power consumption. the 16-bit mn102l (p, f) 25x series contains various peripheral functions and memory interfaces for supporting four chip select (cs) signals and burst rom. this improves high real-time control performance in a wide variety of fields including printers, electric instruments, audiovisual equipment, electric appliances, automobiles, robotics and com- puter peripheral devices. this series adapts a load/store architecture method for comput- ing within registers and a harvard architecture method for separating instructions bus and operand bus. using one byte/one machine cycle basic instructions reduces code size and improves compiler efficiency. mn102 l p xx g rom/ram sizes 25g 128 kb/5 kb 25z 128 kb/3 kb 25d 64 kb/3 kb 25a 32 kb/3 kb 2503 0 kb/3 kb 62g 128 kb/5 kb 62f 96 kb/5 kb 62d 64 kb/5 kb model number internal rom p: otp f: flash none: mask rom core version 16-bit 10200 series mn102l490a input level ttl of mn102l2503 pins refer to "9-2-3 list of pin functions" for details. [model explanation] 1-1-2 features this series contains a flexible and optimized hardware architecture as well as a simple and efficient instruction set. this allows economy and speed. this section describes the features of this series cpu. 1 . linear addressing for large systems the mn10200 series contains up to 16 mbytes of linear address space. the cpu pro- vides an effective development environment without detecting borders between address spaces. the hardware architecture is also optimized for large systems. the memory is not divided into instruction areas and data areas so that operations can share instructions.
3 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 70 conventional register assignment 0 7 new register assignment register specification field register specification field 15 8 2 . single-byte basic instruction length the mn10200 series has replaced general registers with eight internal cpu registers divided four address registers (a0 - a3) and four data registers (d0-d3). the register specification fields are four bits or less, and the code sizes of the frequently used basic instructions including register- to-regis- ter operations and load/store operations are one byte. 3 . high-speed pipeline processing the mn10200 series executes instructions in a 3-stage pipeline: fetch, decode and execute. this allows the mn10200 series to execute instruc- tions of single byte in one machine cycle (100 ns with a 20-mhz oscilla- tor). 4 . simple instruction set the mn10200 series uses an instruction set of 36 instructions, designed specially for the programming model for embedded applications. to compress the code size, instructions have a variable length of one byte to five bytes. the most frequently used instructions in c-language compiler are single byte. 5 . high-speed interrupt response the mn10200 series suspends instruction execution even during the ex- ecution of the instruction with long execution cycles. after an interrupt occurs, the program moves to the interrupt service routine within 11 cycles or less. the mn10200 series improves real-time control performance us- ing the interrupt handler which adjusts interrupt servicing speed depending on user requirements. fetch decode address calculation execute instruction 1 1 cycle fetch decode address calculation execute instruction 2 main program interrupt service routine instruction 1 instruction 2 instruction 3 instruction 4 interrupt request
4 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 6 . flexible interrupt control structure the interrupt controller divides into eight groups (of them, group 0 is reserved for nmi) and supports a maximum of four vectors for each group in total of 26 vectors. each group can be set to one of seven priority levels. this provides the software design flexibility and control. the cpu is compatible with software from previous panasonic peripheral mod- ules. 7 . high-speed, high-functional external interface the mn10200 series supports external interface functions including chip select (cs) sig- nal generation, handshake function and bus arbitration. 8 . c-language development environment the mn10200 series contains highly efficient c compiler and simple hardware optimized for c-language programming. with this advantage, this series improves development environment for c-language embedded applications without expanding the program size. the panaxseries development tools support the mn10200 series devices. 9 . outstanding power savings the mn10200 series contains separate buses which distribute and reduce load capaci- tance. this reduces overall power consumption. the mn10200 series also supports three modes of slow, halt and stop for power savings.
5 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 1-1-3 overview this section describes the basic configuration and function of this series. address space the memory contains up to 16-mbyte linear address space. the instruction area and data area are not separated so that internal ram, special function registers for internal periph- eral functions are allocated into the first 64 kbytes in memory as the basic configuration. three memory modes shown in table 1-1-1 are available depending on models and sizes of user programs. x'0fc000' internal rom internal ram i/o control registers x'ffffff' x'080000' x'010000' x'00fc00' x'008000' x'000000' max of 31 kbytes 1 kbyte max of 496 kbytes external memory external memory external memory 16 mbytes program start address x'080000' interrupt handlerstart address x'080008' figure 1-1-1 address space this is a general example of the memory expansion mode. the start address of internal rom is fixed at x?08000?while the end address of internal rom depending on sizes of internal rom. (the end address in this example is 496 kbytes.) both start address and end address of internal ram are changed within x?08000?to x?0fbff?depending on models. mode address bit width internal rom capacity single-chip mode memory expansion mode processor mode up to 24 bits 16 kbytes or more none table 1-1-1 memory modes
6 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description internal registers, memory and special function registers 23 pc 0 program counter the program counter specifies the address (24 bits) of the program during the execution. 23 a0 0 address registers the address registers specify the data location on the memory. of four reg- isters, a3 is assigned as the stack pointer. a1 a2 a3 the data registers perform all arithmetic and logic operations. when the byte (8-bit) data or the word (16-bit) data is transferred to memory or an- other register, the instruction adds a zero or sign extension. 15 mdr 0 multiplication/division register the multiplication/division register stores the upper 16 bits of the 32-bit product of the multiplication operations. in division operations, this register stores the upper 16 bits of the 32-bit dividend before the execution and the 16-bit remainder of the quotient after the execution. 15 psw 0 processor status word the processor status word indicates the cpu status. this register stores the operation result flags and interrupt mask levels. 23 d0 0 data registers d1 d2 d3 rom ram memory, special registers, i/o ports cpum, memctr, iagr gnicr scnctr, scntrb, scnstr anctr, anbuf tmnmd, tmnbc, tmnbr... memmdn, exmctr atcbc, atcctr pnout, pnin, pndir memory (rom and ram), special registers for controlling peripheral func- tions and i/o ports are assigned to the same address space. internal controlregisters interrupt control registers serial interface a/d converter timers/counters memory control atc controller i/o ports
7 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description interrupt controller the interrupt controller (group 0 to group 7) allocated to the outside of the cpu controls all nonmaskable interrupts and maskable interrupts except reset. each group contains up to four interrupt vectors and specifies any of seven priority levels. 0 1 2 3 4 5 6 interrupt mask nonmaskable interrupt receive reset receive interrupt enable maskable interrupt receive reset cpu core 3 maskable interrupt controller group 1 (g1cir) nonmaskable interrupt controller group 0 (g0cir) 3 maskable interrupts 26 vectors maskable interrupt controller group 7 (g7cir) interrupt controller 3 external pin interrupts peripheral interrupts, etc. nonmaskable interrupts watchdog timers undefined instruction external pin nmi hardware processing push pc, psw interrupt main program x'080008' interrupt service routine reset interrupt vectors at the beginning interrupt preprocessing push registers, branch to entry address, etc. jmp, etc. max. of 4 mashine cycles 7 machine cycles the cpu checks the processor status word status to determine whether an interrupt re- quest is accepted or not. when an interrupt is accepted, automatic servicing by hardware starts and the program counter and psw are pushed to the stack. next, the program moves to the interrupt, searches to the interrupt vector and branches to the entry address of the interrupt service for that interrupt. figure 1-1-2 interrupt controller configuration figure 1-1-3 interrupt servicing sequence
8 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 1-2 basic specifications this section describes the basic specification of this series. please refer to product standards for details. load/store architecture eight registers: four 24-bit data registers four 24-bit address registers others: 24-bit program counter 16-bit processor status word 16-bit multiplication/division register 36 instructions 6 addressing modes one-byte basic instruction length code assignment: 1 to 2 bytes (basic) + 0 to 3 bytes (extension) 10 mhz internal operating frequency with a 20-mhz oscillator clock cycles: for instruction execution, minimum 1 cycle (100 ns) for register-to-register operations, minimum 1 cycle for load/store operations, minimum 1 cycle for branch operations, 1 to 3 cycles 3-stage: instruction fetch, decode, execute 16-mbyte linear address space 24-bit address bus four chip select (cs) signals (fixed addresses) 8- or 16- bit data bus minimum 1 bus cycle (100 ns with a 20-mhz oscillator) set bus width for each 4 mbytes set wait control (handshake setting and fixed wait setting are possible.) support rom burst mode select address/data separate pins or address/data shared pins slow mode, stop mode, halt mode high-speed: up to 20 mhz low-speed: up to 32 khz cpu structure instruction basic performance pipeline address space external bus low-power mode frequency circuit table 1-2-1 basic specifications (1/2)
9 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 26 vectors 3 nonmaskable interrupts 23 maskable interrupts (7 interrupt priority level settings) 6 external interrupts 5 external interrupts (individual irq, edge specification) 1 external nonmaskable interrupt 20 internal interrupts 12 timer interrupts, 4 serial interrupts, 1 atc interrupt, 1 a/d interrupt, 1 watchdog timer interrupt, 1 undefined instruction interrupt six 8-bit timers (down counters) reload timer cascading function (form as 16-bit or 40-bit timer) timer output (duty of 1:1) internal clock source or external clock source serial interface clock generation start timing generation for a/d converter two 16-bit timers (up/down counters) two channels of compare/capture registers internal clock source or external clock source timer output (duty of 1:1) (max. of four channels) pwm/one-shot pulse output (max. of two channels) two-phase encoder input (4x or 1x method) 17-bit watchdog timer 1 channel (fixed between serial channel 0 and internal ram) serial (ch0) transmit/receive interrupt request 600 ns of 1-byte data transfer speed with a 20-mhz oscillator two uart/synchronous (shared) serial interfaces a/d converter eight 8-bit inputs auto scanning (1 to 8 channel settings) 2-byte byte-swap, 3-byte byte-swap, or 4-byte byte-swap 80 i/o ports (all shared pins except rom less) 48 i/o ports (all shared pins, with rom less) 100-pin lqfp table 1-2-1 basic specifications (2/2) interrupt timer/counter atc * serial interface analog interface byte-swap register i/o port package
10 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 1-3 block diagram figure 1-3-1 shows the block diagram including the cpu core and the table 1-3-1 describes the block functions. a1 a0 a3 a2 d1 d0 d3 d2 mdr t1 t2 clock generator clock source instruction execution controller instruction decoder interrupt controller instruction queue interrupt bus internal peripheral function brack breq external interface ram bus internal ram internal rom rom bus bus controller operand address program address program counter alu address registers data registers a b psw multiplication/division register increment peripheral extension bus external expansion bus figure 1-3-1 block diagram
11 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description the clock generator contains the clock oscillation circuit connected to an external crystal and supplies the clock to all cpu blocks. the program counter generates addresses for instruction queues. normally, it increments based on the sequencer indication, but for branch instructions and interrupt acceptance, it sets the branch address or alu operation results. the instruction queue saves up to 4 bytes of prefetched instructions. the instruction decoder decodes the instruction queue content, generates control signals needed for the instruction execution, and executes the instruction by controlling each block in the cpu. the instruction execution controller controls the operations of each cpu function based on results from the instruction decoder and interrupt requests. the alu calculates the operand addresses for arithmetic operations, logic operations, shift operations, register relative indirect addressing, indexed addressing and register in- direct addressing. internal rom and internal ram are allocated as the program, data and stack areas. the address registers (an) store the addresses of memory accessed during data transfer. they also store the base addresses in the register relative indirect, indexed addressing and register indirect addressing modes. the data registers (dn) store the operation results and transfer the data to memory. they also store the operand addresses in indexed addressing and register indirect addressing mode. the multiplication/division register (mdr) stores the data for multiplication/division op- erations. the processor status word (psw) stores the flags that indicate the status of the cpu interrupt controller and operation results. the interrupt controller detects the interrupt requests from the peripheral functions, and requests the cpu to move to the interrupt service routine. the bus controller controls the connection between the cpu internal bus and the cpu external bus. it also contains the bus arbitration function. this series contains the peripheral functions including timers, serial interface and a/d converter. clock generator program counter instruction queue instruction decoder instruction execution controller alu internal rom, internal ram address registers (an) operation registers (dn, mdr) psw interrupt controller bus controller internal peripheral function block function table 1-3-1 block functions
12 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 1-4 pin description 40 41 42 43 44 45 46 47 48 49 50 v dd tm6ioa,p86 tm6ic,p90 tm7ioa,p91 tm7iob,p92 tm7ic,p93 v ss an3,p97 v dd ( vpp ) sbt1,p73 sbo1,p75 nmi sbo0,p72 sbi0,p71 sbt0,p70 an2,p96 an1,p95 an0,p94 tm5io,p85 tm4io,p84 tm3io,p83 sbi1,p74 tm6iob,p87 65 34 35 36 37 38 39 33 24 23 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 22 25 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 74 54 55 56 57 58 59 60 61 62 53 52 51 64 63 75 72 71 70 69 68 67 66 99 98 97 96 95 94 100 mn102l(p,f)25x series (top view) p12,d10,ad10 p11,d09,ad09 p10,d08,ad08 p07,d07,ad07 p05,d05,ad05 p04,d04,ad04 p02,d02,ad02 rst pa1,irq1 p17,d15,ad15 p16,d14,ad14 p15,d13,ad13 p14,d12,ad12 p13,d11,ad11 pa0,irq0 pa2,irq2 pa3,irq3 pa4,irq4 p03,d03,ad03 p06,d06,ad06 v ss p01,d01,ad01 v dd p00,d00,ad00 p22,a02 v dd xo v ss sysclk v dd p23,a03 p56,ale,ale,bstre p55,brack p51,cs1 p63,weh p60,wait p61,re p62,wel p52,cs2 p53,cs3 p54,breq p57,word p20,a00 osci osco mode p50,cs0 xi p21,a01 27 28 29 30 31 32 26 a17,p41 a18,p42 a19,p43 v ss a20,an4,p44 a21,an5,p45 a22,stop,an6,p46 a23,wdout,an7,p47 tm0io,p80 tm1io,p81 tm2io,p82 v dd a12,p34 a13,p35 a14,p36 a15,p37 a16,p40 a11,p33 a05,p25 a06,p26 a07,p27 a08,p30 a09,p31 a10,p32 a04,p24 pa5,adsep * * : use 33 k ? to 50 k ? . * figure 1-4-1 pin configuration the unused input pins are connected to v dd /v ss , the unused output pins are opened and the unused i/o pins are connected to v dd /v ss by setting the direction in ports.
13 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name vdd input/output function description 1-4-1 list of pin functions refer to ?-2-3 list of pin functions?for each pins input level, schmidt and pull-up resistor availability. ttl in the input level column means that the input is determined at ttl level. cmos in the input level column means that the input is determined at cmos level. the column with ?es?sign shows schmidt, while the column with no mark shows no schmidt. pull-up can be programmable with the pull-up control registers. please see ?hapter 8 ports?for details. shared pin power there are six vdd pins. connect these six pins to a power supply of 4.5 v to 5.5 v. vss power (ground) there are four vss pins. connect these four pins to a power supply of 0 v. osci osco high-speed oscillator input (4 mhz to 20 mhz) high-speed oscillator output (4 mhz to 20 mhz) for a self-excited oscillator configuration, connect crystal or ceramic oscillator across these two pins. they have a built-in feedback resistor between them. for stability, insert capacitor of 20 pf to 33 pf be- tween the osci or osco pin and vss pin. (for the exact capacitance, consult the oscillator manufac- turer.) for an external oscillator configuration, connect the osci pin to an oscillator with an amplitude of 4 mhz to 20 mhz and the width between vdd and vss. leave the osco open. see ?igure 1-4-2? connecting the osco pin with the external circuit is not allowed. select the sysclk pin as a synchro- nous signal. input output for a self-excited oscillator configuration, connect crystal or ceramic oscillator across these two pins. they have a built-in feedback resistor between them. for stability, insert capacitor of 100 pf to 200 pf be- tween the xi or xo pin and vss pin. (for the exact capacitance, consult the oscillator manufacturer.) see ?igure 1-4-3? for an external oscillator configuration, connect the xi pin to an oscillator with an amplitude of 32 khz to 200 khz and the width between vdd and vss. leave the xo open. see ?igure 1-4-3? if these pins are not used, fix xi to vdd or vss and leave xo open. connecting the xo pin with the ex- ternal circuit is not allowed. select the sysclk pin as a synchronous signal. table 1-4-1 list of pin functions (1/9) xi xo low-speed oscillator input (32 khz to 200 khz) low-speed oscillator output (32 khz to 200 khz) input output
14 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name rst input/output function description shared pin reset input this pin resets the chip. with a 20-mhz oscillator, reset starts when the low level is input to this pin for more than 400 ns. reset starts even when the noise is input to this pin for less than 400 ns. reset is released when the high level is input to the pin. the oscillation waits of the high-speed oscillation pin (osci) are performed (approximately 6 ms to 7 ms with a 20-mhz oscillator). after that, the chip starts executing the instruction from x?8000? see ?igure 1-4-4? this pin provides the system clock. after reset re- lease, the oscillation waits of osci are always per- formed and this pin outputs the clock of 10 mhz. this pin hold the high level until the oscillation waits are released after the rst pin became the low level. table 1-4-1 list of pin functions (2/9) mode memory mode setup input input input this pin sets either processor mode or single-chip mode (memory expansion mode). pulling the pin low sets the processor mode and internal rom area becomes the external memory area. pulling the pin high sets the single-chip mode (memory expansion mode). see ?-1-1, 2-2-3 memory expansion mode? do not change the mode setting in this pin during operation. when the setting is changed, proper op- eration cannot be guaranteed. in the mn102l2503 (rom less), this pin is fixed the low level. this pin can be used as a general-purpose input/out- put port only in the single-chip mode. see ?hapter 8 ports? in processor mode or memory expansion mode, this pin sets either 8-bit data bus width or 16-bit data bus width in block 0 (the address of x?10000?to x?fffff? of 4 blocks (block 0 to block 3) divided in the 16-mb space. the data bus widths for internal rom, ram and special registers are 16-bit width regardless of this pin setting. pulling the pin low sets the 16-bit data bus width while pulling the pin high sets the 8-bit data bus width. in processor mode or memory expansion mode, al- ways use this pin as an input pin for specifying the data bus width. do not change the data bus width in this pin during operation. when the setting is changed, proper op- eration cannot be guaranteed. sysclk system clock output output p57 general-purpose port 5 data bus width setup input i/o word
15 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name p54 p55 input/output function description shared pin general-purpose port 5 bus request general-purpose port 5 bus request enable output this pin can be used as a general-purpose input/out- put port. see ?hapter 8 ports? the breq and brack pins operate bus arbitration. pulling the breq pin low suspends the execution of the current instruction. after that, the cpu releases bus and pulls the brack pin low. while the cpu is accessing bus, the cpu releases the bus after the bus access is completed and then pulls the brack pin low. pulling the breq pin high restores the bus master to the cpu. see ?-2-2 external memory connection example? table 1-4-1 list of pin functions (3/9) p62 p63 p61 general-purpose port 6 lower byte write en- able output general-purpose port 6 upper byte write en- able output general-purpose port 6 read enable output i/o output i/o output i/o output i/o input i/o output this pin can be used as a general-purpose input/out- put port. see ?hapter 8 ports? these pins provide control signals for the memory read/write. when connecting sram and rom, connect re to oe in memory. re outputs low level during read operation and the cpu read out the content of the memory. when connecting sram, connect wel and weh to we pins in memory. wel and weh output low level during write operation and the cpu writes the data to the memory. weh controls writ- ing of d15 to d08 while wel controls writing of d00 to d07. wel is invalid and used as a general- purpose port 6 when 8-bit bus width for the external memory space is selected in the memory expansion mode. these pins become wel, weh and re pins in the processor mode. (it means these cannot be used as general-purpose ports.) during bus request, stop mode or halt mode, these pins become in a high impedance state. (when using as ports, these are not in a high impedance state.) see ?-2-, 2-2-4 external memory connection ex- ample? wel weh re breq brack
16 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name p43 to p40 input/output function description shared pin general-purpose port 4 address output when using as general-purpose input/output ports, the i/o direction is controlled in bit units. see ?hap- ter 8 ports? those pins output addresses (a19 to a16) of memory in processor mode or memory expansion mode. con- nect them to address pins of memory or address de- code circuit. when they are not accessing the memory, they output undefined addresses. (they output the some fixed values.) during the processor mode, these pins function as a19 to a16, and cannot be used as general-purpose i/o ports. during a bus request (breq is low level), stop mode or halt mode, these pins will be in a high impedance state. (however, these pins will not be in a high impedance state when they are using as general-purpose i/o ports.) table 1-4-1 list of pin functions (4/9) i/o output when using as general-purpose input/output ports, the i/o direction is controlled in bit units. these pins are used as a/d conversion input pins. see ?hapter 6 a/d converter? these pins output addresses (a21 to a20) of memory in processor mode or memory expansion mode. con- nect them to address pins of memory or address de- code circuit. when they are not accessing the memory, they output undefined addresses. (they output the some fixed values.) during the processor mode, these pins function as a21 to a20, and cannot be used as general-purpose i/o ports. during a bus request (breq is low level), stop mode or halt mode, these pins will be in a high impedance state. (however, these pins will not be in a high impedance state when they are using as general-purpose i/o ports or analog input pins.) a19 to a16 p45 to p44 general-purpose port 4 a/d converter input address output i/o input output an5 to an4 a19 to a16
17 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name p46 input/output function description shared pin general-purpose port 4 a/d conversion input stop status signal address output when using as a general-purpose input/output port, the i/o direction is controlled in bit units. this pin is used as an a/d conversion input pin. see ?hapter 6 a/d converter? this pin becomes high level during stop or halt mode. this pin outputs the address (a22) of memory in pro- cessor mode or memory expansion mode. connect it to address pin of memory or address decode cir- cuit. when it is not accessing the memory, it outputs undefined address. (it outputs the any fixed value.) during a bus request (breq is low level), stop mode or halt mode, this pin will be in a high im- pedance state. (however, it will not be in a high im- pedance state when they are using as a general-pur- pose i/o port, an analog input or stop pin.) table 1-4-1 list of pin functions (5/9) i/o input output output when using as a general-purpose input/output port, the i/o direction is controlled in bit units. this pin is used as an a/d conversion input pin. see ?hapter 6 a/d converter? this pin outputs a pulse when the watchdog timer overflows. this pin outputs the address (a23) of memory in pro- cessor mode or memory expansion mode. connect it to address pin of memory or address decode cir- cuit. when it is not accessing the memory, it outputs undefined address. (it outputs the any fixed value.) during a bus request (breq is low level), stop mode or halt mode, this pin will be in a high im- pedance state. (however, it will not be in a high im- pedance state when they are using as a general-pur- pose i/o port, an analog input or wdout pin.) an6 stop a22 p47 general-purpose port 4 a/d converter input watchdog timer over- flow signal address output i/o input output output an7 wdout a23
18 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name p37 to p30 input/output function description shared pin general-purpose port 3 address output when using as general-purpose input/output ports, the i/o direction is controlled in bit units. see ?hap- ter 8 ports? these pins output addresses (a15 to a08) of memory in processor mode or memory expansion mode. con- nect them to address pins of memory or address de- code circuit. when they are not accessing the memory, they output undefined addresses. (they output the some fixed values.) during the processor mode, these pins function as a15 to a08, and cannot be used as general-purpose i/o ports. during a bus request (breq is low level), stop mode or halt mode, these pins will be in a high impedance state. (however, these pins will not be in a high impedance state when they are using as general-purpose i/o ports.) table 1-4-1 list of pin functions (6/9) i/o output when using as general-purpose input/output ports, the i/o direction is controlled in bit units. see ?hap- ter 8 ports? these pins output addresses (a07 to a00) of memory in processor mode or memory expansion mode. con- nect them to address pins of memory or address de- code circuit. when they are not accessing the memory, they output undefined addresses. (they output the some fixed values.) during the processor mode, these pins function as a07 to a00, and cannot be used as general-purpose i/o ports. during a bus request (breq is low level), stop mode or halt mode, these pins will be in a high impedance state. (however, these pins will not be in a high impedance state when they are using as general-purpose i/o ports.) a15 to a08 p27 to p20 general-purpose port 2 address output i/o output a07 to a00
19 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name p17 to p10 p07 to p00 input/output function description shared pin general-purpose port 1 general-purpose port 0 data (address/data) i/o pin when using as general-purpose input/output ports, the i/o direction is controlled in bit units. see ?hap- ter 8 ports? in processor mode or memory expansion mode, these pins function as data input/output during address/ data separate mode, and these pins time-divide the address (the lower 16-bit) output of memory and data input.output during address/data shared mode. when they are not accessing the memory, they become in- put. when the 8-bit data bus width is selected in memory expansion mode or address/data separate mode, p07 to p00 can function as i/o ports. see ?-2-2, 2-2-4 external memory connection during a bus request (breq is low level), stop mode or halt mode, these pins will be in a high impedance state. (however, these pins will not be in a high impedance state when they are using as general-purpose i/o ports.) table 1-4-1 list of pin functions (7/9) i/o i/o when using as general-purpose input/output ports, the i/o direction is controlled in bit units. see ?hap- ter 8 ports? connect cs3 to cs0 to each corresponding cs pin of the memory when accessing sram and rom. see ?hapter 2 bus interface? for address allocation for cs3 to cs0. cs0 cannot be output when accesssing internal rom. during a bus request (breq is low level), stop mode or halt mode, these pins will be in a high impedance state. (however, these pins will not be in a high impedance state when they are using as gen- eral-purpose i/o ports.) d15 to d00 (ad15 to ad00) p53 to p50 general-purpose port 5 chip select output i/o output cs3 to cs0 this pin can be used as a general-purpose input/out- put port only during single-chip mode. see ?hapter 8 ports? this pin sets either address/data separate mode or address/data shared mode in processor mode or memory expansion mode. pulling the pin high sets the address/data separate mode while pulling the pin low sets the address/data shared mode. always use as adsep in processor mode or memory expansion mode. do not change this pins setting during the operation. when the setting is changed, proper operation can- not be guaranteed. pa5 general-purpose port a addree/data separate/ shared mode setup i/o input adsep
20 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name p56 input/output function description shared pin general-purpose port 5 read enable for burst rom (address latch enable output) this pin can be used as a general-purpose input/out- put port. see ?hapter 8 ports? this pin becomes a re signal for burst rom during the address/data separate mode in processor mode. (however, this pin is not used as bstre because connecting the re pin to burst rom is possible with the penalty for burst rom.) see ?-1-3 rom burst mode timing this pin provides a timing signal of latching the ad- dress which outputs to a15 to a00 during the ad- dress/data shred mode. ale outputs at positive logic at reset release, but the register switches to negative logic. because of this, ale cannot be used at nega- tive logic in rom less or processor mode. ale can be output even during cycles when ale is not ac- cessing the external device. during a bus request (breq is low level), stop mode or halt mode, this pin will be in a high im- pedance state. (however, this pin will not be in a high impedance state when it is using as a general- purpose i/o port.) table 1-4-1 list of pin functions (8/9) i/o output this pin can be used as a general-purpose input/out- put port. see ?hapter 8 ports? this pin extends the cycle of accessing to the exter- nal memory when the external memory wait is set to handshake mode. pulling this pin low ends access to the external memory. see ?igure 1-4-5 bstre (ale/ale) p60 general-purpose port 6 bus cycle wiat input i/o input wa i t these pins can be used as general-purpose input/out- put ports. see ?hapter 8 ports? these pins can be used as data input/output for serial interface. when these are unused, the input pins are fixed as high level while the output pins are opened. see ?hapter 5 serial interface? p74, p71 general-purpose port 7 serial interface data in- put i/o input sbi1 to sbi0 p75, p72 general-purpose port 7 serial interface data output i/o output sbo1 to sbo0 these pins can be used as general-purpose input/out- put ports. see ?hapter 8 ports? these pins can be used as synchronous transfer clock signals for serial interface. when these are unused, the input pins are fixed as high level while the output pins are opened. see ?hapter 5 serial interface? p70 general-purpose port 7 serial interface 0 clock input/output i/o i/o sbt0 p73 general-purpose port 7 serial interface 1 clock input/output i/o i/o sbt1
21 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description pin name p85 to p80 input/output function description shared pin general-purpose port 8 timer 5 to timer 0 in- put/output when using as general-purpose input/output ports, the i/o direction is controlled in bit units. see ?hap- ter 8 ports? these pins can be used as timer 5 to timer 0 input/ output pins. table 1-4-1 list of pin functions (9/9) i/o i/o tm5io to tm0io p86 timer 6a input/output this pin can be used as a general-purpose input/out- put port. this pin can be used as a timer input capture input/ output compare output pin. i/o i/o tm6ioa p87 timer 6b input/output this pin can be used as a general-purpose input/out- put port. this pin can be used as a timer input capture input/ output compare output pin. i/o i/o tm6iob p90 timer 6 counter clear this pin can be used as a general-purpose input/out- put port. this pin can be used as a timer 6 counter clear pin. see ?hapter 4 timers i/o input tm6ic p91 timer 7a input/output this pin can be used as a general-purpose input/out- put port. this pin can be used as a timer input capture input/ output compare output pin. i/o i/o tm7ioa p92 general-purpose port 8 timer 7b input/output this pin can be used as a general-purpose input/out- put port. this pin can be used as a timer input capture input/ output compare output pin. i/o i/o tm7iob p93 timer 7 counter clear this pin can be used as a general-purpose input/out- put port. this pin can be used as a timer 7 counter clear pin. see ?hapter 4 timers i/o input tm7ic p97 to p94 general-purpose port 9 a/d conversion input when using as a general-purpose input/output port, the i/o direction is controlled in bit units. this pin is used as an a/d conversion input pin. see ?hapter 6 a/d converter? i/o input an3 to an0 nmi nmi a nmi interrupt occurs on the falling edge to low level at negative logic. ( when reading the port a, monitor the pin value at bit 6.) input pa4 to pa0 general-purpose port a external interrupt when using as a general-purpose input/output port, the i/o direction is controlled in bit units. see ?hap- ter 8 ports? i/o input irq4 to irq0
22 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 20 pf to 33 pf 20 pf to 33 pf osci osco 4 mhz to 20 mhz osci osco 4 mhz to 20 mhz oscillation circuit figure 1-4-2 osci and osco connection example xi xo 32 khz to 200 khz oscillation circuit 100 pf to 200 pf 100 pf to 200 pf xi xo 32 khz to 200 khz figure 1-4-3 xi and xo connection example figure 1-4-4 reset connection example 10 k ? to 50 k ? + - 10 f to 100 f rst sw di re weh wel wait reset delay circuit figure 1-4-5 wait signal control circuit example
23 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description 1-5 external dimensions package code: lqfp100-p-1414 body material: epoxy resin, lead material: feni42 alloy, lead finish method: solder plating figure 1-5-1 external dimensions: 100-pin lqfp external dimensions are subject to change. before using, please contact your nearest sales office for the latest product specifications.
24 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 1 general description
0 1 2 3 4 5 6 7 8 9 chapter 2 bus interface
26 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 2-1 bus interface 2-1-1 overview this series contains three memory modes of single-chip mode, memory expansion mode and processor mode. the chip of this series connects to the external memory or i/o consisted of gate array in the expansion mode or processor mode. the address space is divided into four fixed areas (block 0 to block 3). each block has approximately 4 mb area and generates four chip-select signals to its corresponding external space. (the address space is optionally divided when the chip-select signals are generated externally.) 16-bit bus width or 8-bit bus width is selected for each block. the word pin sets the 16- bit bus width or 8-bit bus width for block 0 where the reset handler exists. on the other hand, the memmdn register sets the bus width for block 1 to block 3. see ?-4 pin functions for pin setting. x'000000' x'00e000' x'00ec00' or x'00f400' x'00fc00' x'010000' x'800000' x'c00000' x'ffffff' x'100000' x'080000' or x'088000' or x'090000' or x'0a0000' x'400000' internal ram (5 kb or 3 kb) access prohibited area (2 kb or 4 kb) special registers (1 kb) external memory (448 kb) internal rom (128 kb or 64 kb or 32 kb or 0kb) external memory (3952 kb) external memory (4 mb) external memory (4 mb) external memory (4 mb) external memory (384 kb or 448 kb or 480 kb or 512 kb) x'080000' cs0 area burst rom support area cs1 area cs2 area cs3 area block 1 block 2 block 3 block 0 (56 kb) virtual image (56 kb) actual image external memory external memory figure 2-1-1 address space the mn102l2503 has only proces- sor mode. * accessing the virtual area using the program means accessing the real area in this series.
27 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface x'09ffff' x'ffffff' x'00ffff' x'00fc00' x'00f3ff' x'000000' x'080000' x'00e000' single-chip mode pin mode = 'h' memory expansion mode reset handler interrupt handler pin mode = 'h' after reset, set ports 0,1,2,3,4,5,6 to a23 -a00, d15 - d00 and bus interface signals using software. processor mode reset handler interrupt handler pin mode = 'l' access prohibited area access prohibited area internal ram internal rom access prohibited area access prohibited area external memory external memory internal ram internal rom access prohibited area external memory external memory internal ram access prohibited area external memory reset handler interrupt handler external memory special registers special registers special registers figure 2-1-2 bus controller in this series, the addresses of x?00000?to x?0dfff?replaces the addresses of x?00000 to x?0dfff? beacuse of this, the cs2 signal is generated even though the program accesses the address of x?00000 to x?0dfff shown in figure 2-1-1. the cs1 pin, cs2 pin and cs3 pin are allocated into block1, block2 and block 3 respectively, and these pins become low level. x?10000?to x?fffff (the cs0 signal is not generated in the internal rom area.) x?00000?to x?fffff x?00000?to x?0dfff x?00000?to x?fffff x?00000?to x?fffff cs0 cs1 cs2 cs3 table 2-1-1 cs signal generation this series has two modes of address/data shared mode and address/data separated mode. the adsep pin selects each mode. figure 2-1-3 to figure 2-1-7 show the pin configura- tion in each mode. figure 2-1-2 shows the bus control- ler of the mn102l25g. the cs0 signal is generated even in the internal rom area during pro- cessor mode. accessing the logical addresses of x?00000?to x?0dfff?means ac- cessing the addresses of x?00000 to x?0dfff?
28 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 40 41 42 43 44 45 46 47 48 49 50 v dd tm6ioa,p86 tm6ic,p90 tm7ioa,p91 tm7iob,p92 tm7ic,p93 v ss an3,p97 v dd ( vpp ) sbt1,p73 sbo1,p75 nmi sbo0,p72 sbi0,p71 sbt0,p70 an2,p96 an1,p95 an0,p94 tm5io,p85 tm4io,p84 tm3io,p83 sbi1,p74 tm6iob,p87 65 34 35 36 37 38 39 33 24 23 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 22 25 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 74 54 55 56 57 58 59 60 61 62 53 52 91 64 63 75 72 71 70 69 68 67 66 99 98 97 96 95 94 100 MN102L25X (top view) 100 -pin lqfp rst pa1,irq1 pa0,irq0 pa2,irq2 pa3,irq3 pa4,irq4 p22 v dd xo v ss sysclk v dd p23 ale,ale p55,brack p51,cs1 weh p60,wait re p62,wel p52,cs2 p53,cs3 p54,breq word p20 osci osco p50,cs0 xi p21 27 28 29 30 31 32 26 a17,p41 a18,p42 a19,p43 v ss a20,an4,p44 a21,an5,p45 a22,stop,an6,p46 a23,wdout,an7,p47 tm0io,p80 tm1io,p81 tm2io,p82 v dd p34 p35 p36 p37 a16,p40 p33 p25 p26 p27 p30 p31 p32 p24 ad10 ad09 ad08 ad07 ad05 ad04 ad02 ad15 ad14 ad13 ad12 ad11 ad03 ad06 v ss ad01 v dd ad00 figure 2-1-3 memory expansion mode (address/data shared pin configuration) 40 41 42 43 44 45 46 47 48 49 50 v dd tm6ioa,p86 tm6ic,p90 tm7ioa,p91 tm7iob,p92 tm7ic,p93 v ss an3,p97 v dd ( vpp ) sbt1,p73 sbo1,p75 nmi sbo0,p72 sbi0,p71 sbt0,p70 an2,p96 an1,p95 an0,p94 tm5io,p85 tm4io,p84 tm3io,p83 sbi1,p74 tm6iob,p87 65 34 35 36 37 38 39 33 24 23 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 22 25 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 74 54 55 56 57 58 59 60 61 62 53 52 91 64 63 75 72 71 70 69 68 67 66 99 98 97 96 95 94 100 MN102L25X (top view) 100-pin lqfp rst pa1,irq1 pa0,irq0 pa2,irq2 pa3,irq3 pa4,irq4 p22,a02 v dd xo v ss sysclk v dd p23,a03 p56,bstre p55,brack p51,cs1 weh p60,wait re p62,wel p52,cs2 p53,cs3 p54,breq word p20,a00 osci osco p50,cs0 xi p21,a01 27 28 29 30 31 32 26 a17,p41 a18,p42 a19,p43 v ss a20,an4,p44 a21,an5,p45 a22,stop,an6,p46 a23,wdout,an7,p47 tm0io,p80 tm1io,p81 tm2io,p82 v dd a12,p34 a13,p35 a14,p36 a15,p37 a16,p40 a11,p33 a05,p25 a06,p26 a07,p27 a08,p30 a09,p31 a10,p32 a04,p24 d10 d09 d08 p07,d07 p05,d05 p04,d04 p02,d02 d15 d14 d13 d12 d11 p03,d03 p06,d06 v ss p01,d01 v dd p00,d00 figure 2-1-4 memory expansion mode (address/data separated pin configuration)
29 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 40 41 42 43 44 45 46 47 48 49 50 v dd tm6ioa,p86 tm6ic,p90 tm7ioa,p91 tm7iob,p92 tm7ic,p93 v ss an3,p97 v dd ( vpp ) sbt1,p73 sbo1,p75 nmi sbo0,p72 sbi0,p71 sbt0,p70 an2,p96 an1,p95 an0,p94 tm5io,p85 tm4io,p84 tm3io,p83 sbi1,p74 tm6iob,p87 65 34 35 36 37 38 39 33 24 23 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 22 25 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 74 54 55 56 57 58 59 60 61 62 53 52 91 64 63 75 72 71 70 69 68 67 66 99 98 97 96 95 94 100 MN102L25X (top view) 100-pin lqfp ad10 ad09 ad08 ad07 ad05 ad04 ad02 rst pa1,irq1 ad15 ad14 ad13 ad12 ad11 pa0,irq0 pa2,irq2 pa3,irq3 pa4,irq4 ad03 ad06 v ss ad01 v dd ad00 v dd xo v ss sysclk v dd osci osco xi 27 28 29 30 31 32 26 a17 a18 a19 v ss a20 a21 a22,stop,an6,p46 a23,wdout,an7,p47 tm0io,p80 tm1io,p81 tm2io,p82 v dd p34 p35 p36 p37 a16 p33 p25 p26 p27 p30 p31 p32 p24 p22 p23 ale p55,brack cs1 weh p60,wait re wel cs2 cs3 p54,breq word p20 cs0 p21 figure 2-1-5 processor mode (address/data shared pin configuration) 40 41 42 43 44 45 46 47 48 49 50 v dd tm6ioa,p86 tm6ic,p90 tm7ioa,p91 tm7iob,p92 tm7ic,p93 v ss an3,p97 v dd ( vpp ) sbt1,p73 sbo1,p75 nmi sbo0,p72 sbi0,p71 sbt0,p70 an2,p96 an1,p95 an0,p94 tm5io,p85 tm4io,p84 tm3io,p83 sbi1,p74 tm6iob,p87 65 34 35 36 37 38 39 33 24 23 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 22 25 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 74 54 55 56 57 58 59 60 61 62 53 52 91 64 63 75 72 71 70 69 68 67 66 99 98 97 96 95 94 100 MN102L25X (top view) 100-pin lqfp d10 d09 d08 p07,d07 p05,d05 p04,d04 p02,d02 rst pa1,irq1 d15 d14 d13 d12 d11 pa0,irq0 pa2,irq2 pa3,irq3 pa4,irq4 p03,d03 p06,d06 v ss p01,d01 v dd p00,d00 a02 v dd xo v ss sysclk v dd a03 bstre p55,brack cs1 weh p60,wait re wel cs2 cs3 p54,breq word a00 osci osco cs0 xi a01 27 28 29 30 31 32 26 a17 a18 a19 v ss a20 a21 a22,stop,an6,p46 a23,wdout,an7,p47 tm0io,p80 tm1io,p81 tm2io,p82 v dd a12 a13 a14 a15 a16 a11 a05 a06 a07 a08 a09 a10 a04 figure 2-1-6 processor mode (address/data separated pin configuration) ale is not generated during proces- sor mode.
30 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 40 41 42 43 44 45 46 47 48 49 50 v dd tm6ioa,p86 tm6ic,p90 tm7ioa,p91 tm7iob,p92 tm7ic,p93 v ss an3,p97 v dd ( vpp ) sbt1,p73 sbo1,p75 nmi sbo0,p72 sbi0,p71 sbt0,p70 an2,p96 an1,p95 an0,p94 tm5io,p85 tm4io,p84 tm3io,p83 sbi1,p74 tm6iob,p87 65 34 35 36 37 38 39 33 24 23 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 22 25 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 74 54 55 56 57 58 59 60 61 62 53 52 91 64 63 75 72 71 70 69 68 67 66 99 98 97 96 95 94 100 MN102L25X (top view) 100-pin lqfp p12 p11 p10 rst pa1,irq1 p17 p16 p15 p14 p13 pa0,irq0 pa2,irq2 pa3,irq3 pa4,irq4 v ss v dd p07 p05 p04 p02 p03 p06 p01 p00 p22 v dd xo v ss sysclk v dd p23 p56 p55 p51 p63 p60 p61 p62 p52 p53 p54 p57 p20 osci osco p50 xi p21 27 28 29 30 31 32 26 p41 p42 p43 v ss an4,p44 an5,p45 stop,an6,p46 wdout,an7,p47 tm0io,p80 tm1io,p81 tm2io,p82 v dd p34 p35 p36 p37 p40 p33 p25 p26 p27 p30 p31 p32 p24 pa5 figure 2-1-7 single-chip mode
31 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface
32 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 2-1-2 control registers these registers control the bus interface: the memory control register (memctr), the memory moode control register (memmdn) and the ex- ternal memory control register (exmctr). r e t s i g e rs s e r d d aw / rn o i t c n u f r t c m e m' 2 0 c f 0 0 ' xw / rr e t s i g e r l o r t n o c y r o m e m 0 d m m e m' 0 3 c f 0 0 ' xw / r0 r e t s i g e r l o r t n o c e d o m y r o m e m 1 d m m e m' 2 3 c f 0 0 ' xw / r1 r e t s i g e r l o r t n o c e d o m y r o m e m 2 d m m e m' 4 3 c f 0 0 ' xw / r2 r e t s i g e r l o r t n o c e d o m y r o m e m 3 d m m e m' 6 3 c f 0 0 ' xw / r3 r e t s i g e r l o r t n o c e d o m y r o m e m r t c m x e' 0 0 d f 0 0 ' xw / rr e t s i g e r l o r t n o c y r o m e m l a n r e t x e table 2-1-2 list of bus interface control registers the memctr register and the memmdn register need to set the conditions matched the system configuration during the initialization program. [see 9-4 initialization pro- gram ] the memctr register sets x 04n0 (n = 0 to 3, the wait cycle of special registers is normally 1) during the initialization program. the memmd0 register sets the wait cycle for the device connected to block 0. the bits for selecting bus mode do noe exist in the memmd0 register like other memmdn reg- isters because the bus width for block 0 is selected using the pin. setting the wait[1:0] is ignored in the burst rom support area when using burst rom. 15 14 13 12 11 10 9 7 6 4 3 2 1 0 8 5 wait 1 wait 0 wait cycle setting for block 0 00: none 01: 1 cycle 10: 2 cycles 11: handshake memmd0: x?0fc30
33 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface the memmd1 register sets the wait cycles and bus mode for block 1. 15 14 13 12 11 10 9 7 6 4 3 2 1 0 8 5 wait 1 wait 0 wait cycle setting for block 1 00: none 01: 1 cycle 10: 2 cycles 11: handshake bsmod bus width setting for block 1 0: 16-bit bus width 1: 8-bit bus width memmd1: x?0fc32 the memmd2 register sets the wait cycles and bus mode for block 2. when using the address converted area (x 000000 to x 00dfff ), set the bus width for block 2 as the same as the bus width for block 0. 15 14 13 12 11 10 9 7 6 4 3 2 1 0 8 5 wait 1 wait 0 wait cycle setting for block 2 00: none 01: 1 cycle 10: 2 cycles 11: handshake bsmod bus width setting for block 2 0: 16-bit bus width 1: 8-bit bus width memmd2: x?0fc34 the memmd3 register sets the wait cycles and bus mode for block 3. 15 14 13 12 11 10 9 7 6 4 3 2 1 0 8 5 wait 1 wait 0 wait cycle setting for block 3 00: none 01: 1 cycle 10: 2 cycles 11: handshake bsmod bus width setting for block 3 0: 16-bit bus width 1: 8-bit bus width memmd3: x?0fc36
34 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface the exmctr register sets the burst mode for rom, the polarity of ale signal during the address/data shared mode, and the pulse width of weh signal and wel signal. 15 14 13 12 11 10 9 7 6 43 2 10 8 5 ale siganl polarity 0: pogitive logic 1: negative logic brpg 0 brpg 1 we sht page size of rom burst mode 00: 4 bytes 01: 8 bytes 10: 16 bytes 11: reserved rom burst mode 00: disable 01: reserved 10: enable (without penalty) 11: enable (with penalty) (*3) (*2) weh, wel pulse width shortening 0: disable 1: enable (*1) nale en bren 1 bren 0 exmctr: x?0fd00 *3 see 2-1-3 rom burst mode timing for the penalty availability of burst mode. rom burst mode without penalty is not allowed dur- ing processor mode or in the mn102l2503. *2 setting the naleen bit is in- valid during the address/data sepa- rated mode. *1 setting the wesht bit to 1 makes the rising edge of weh and wel 1/4 cycle (25 ns with a 20- mhz oscillator) forward and the hold time of address/data longer.
35 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface
36 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 2-1-3 rom burst mode timing this lsi series supports interface for rom corresponding to burst mode accesses. the burst mode is a mode which reads the data of consecutive few bytes (only few lower bits are changed) at high-speed (access twice faster than normal access). this series supports the lower 2 bits (4 bytes for page size), the lower 3 bits (8 bytes for page size), and the lower 4 bits (16 bytes for page size). an - a02 ce oe a01 - 00 d07 - 00 figure 2-1-8 rom timing for burst mode (4 bytes for page size) use burst mode only during the ad- dress/data separated mode. (do not use burst mode during the address/ data shared mode.) access area for burst mode is x 080000 to x 0fffff . the ac- cess cycle in x 080000 to x 0fffff is 1 wait cycle outside the page and no wait cycle in the page. (bits[1:0] of the memmd0 regis- ter are ignored.)
37 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface this series has the access cycle with penalty and without penalty when the chip accesses to devices except rom after it accesses to rom during the burst mode. figure 2-1-9 shows their timings and figure 2-1-10 shows the connection example. the rom burst mode is used only during the address/data separated mode and the wait pin is ignored even though handshake mode us selected. (figure 2-1-9 shows the timing of 8 bytes/page during the 16-bit bus mode.) osci sysclk a23-00 d15-00 cs0 csn re weh wel (a2-0=000) (a2-0=010)(a2-0=100)(a2-0=110) (penarty)(not rom) (a2-0=000) osci sysclk a23-00 d15-00 cs0 csn bre re weh wel (a2-0=000) (a2-0=010)(a2-0=100)(a2-0=110) (not rom) (a2-0=000) (a2-0=010) with penalty without penalty figure 2-1-9 rom burst mode access timing when the access without penalty is selected, accessing x 010000 to x 07ffff and x 100000 to x 3fffff is not allowed.
38 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface weh (wel) csn oe ce a23-00 d15-00 ad oe wr ce ram cs0 re MN102L25X weh (wel) csn a23-00 d15-00 cs0 re MN102L25X oe ce ad oe wr ce ram bstre oe *note *note: when using rom with longer output data hold time, you may need to equip the 3-state buffer (for example, 74als541) in the broken line. a rom d a rom d figure 2-1-10 access timing memory connection example during rom burst mode as figure 2-1-10 shows, the access is fast but re signal (bstre) for burst rom is required when access without penalty cycle is selected. in addition, the external 3-state buffer (for example, 74als541) may be required when the rom data hold time is long.
39 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface
40 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface no. 1 up to 16 bytes 8 bit p0dir= -------* p0md= -------* use d07 to d00 as general-purpose ports. (a03 to a00) (d15 to d08) p1dir= -------0 p1md= -------1 p2dir= ---*---0 p2md= ---0---1 use a23 to a04 as general-purpose ports. p3dir= ******** p3md= 00000000 p4dir= ******** p4md= 00000000 16 bit p0dir= -------0 p0md= -------1 use a23 to a04 as general-purpose ports. (d15 to d00) p1dir to p4dir and p1md to p4md are same as those in the above 8-bit bus width of no. 1. no. 2 up to 256 bytes 8 bit p0dir= -------* p0md= -------* use d07 to d00 as general-purpose ports. (a07 to a00) (d15 to d08) p1dir= -------0 p1md= -------1 use a23 to a08 as general-purpose ports. p2dir= ---0---0 p2md= ---1---1 p3dir to p4dir and p1md to p4md are same as those in the above 8-bit bus width of no. 1. 16 bit p0dir= -------0 p0md= -------1 use a23 to a08 as general-purpose ports. (d15 to d00) p1dir to p4dir and p1md to p4md are same as those in the above 8-bit bus width. p0dir to p2dir, p4dir and p0md to p2md, p4md are no.3 up to 512 bytes 8 bit same as those in the above 8-bit bus width of no. 1. use d07 to d00 as general-purpose ports. (a08 to a00) (d15 to d08) p3dir= *******0 p3md= 00000001 use a23 to a09 as general-purpose ports. 16 bit p0dir to p2dir, p4dir and p0md to p2md, p4md are use a23 to a09 as general-purpose ports. (d15 to d00) same as those in the above 16-bit bus width of no. 1. p3dir and p3md are same as those in the above 8-bit bus width. p0dir to p2dir, p4dir and p0md to p2md, p4md are no.4 up to 1k bytes 8bit same as those in the above 8-bit bus width of no. 1. use d07 to d00 as general-purpose ports. (a09 to a00) (d15 to d08) p3dir= ******00 p3md= 00000011 use a23 to a10 as general-purpose ports. 16bit p0dir to p2dir, p4dir and p0md to p2md, p4md are use a23 to a10 as general-purpose ports. (d15 to d00) same as those in the above 16-bit bus width of no. 1. p3dir and p3md are same as those in the above 8-bit bus width. p0dir to p2dir, p4dir and p0md to p2md, p4md are no.5 up to 2k bytes 8bit same as those in the above 8-bit bus width of no. 1. use d07 to d00 as general-purpose ports. (a10 to a00) (d15 to d08) p3dir= *****000 p3md= 00000111 use a23 to a11 as general-purpose ports. 16bit p0dir to p2dir, p4dir and p0md to p2md, p4md are use a23 to a11 as general-purpose ports. (d15 to d00) same as those in the above 16-bit bus width of no. 1. p3dir and p3md are same as those in the above 8-bit bus width. p0dir to p2dir, p4dir and p0md to p2md, p4md are no.6 up to 4k bytes 8bit same as those in the above 8-bit bus width of no. 1. use d07 to d00 as general-purpose ports. (a11 to a00) (d15 to d08) p3dir= ****0000 p3md= 00001111 use a23 to a12 as general-purpose ports. 16bit p0dir to p2dir, p4dir and p0md to p2md, p4md are use a23 to a12 as general-purpose ports. (d15 to d00) same as those in the above 16-bit bus width of no. 1. p3dir and p3md are same as those in the above 8-bit bus width. p0dir to p2dir, p4dir and p0md to p2md, p4md are no.7 up to 8k bytes 8bit same as those in the above 8-bit bus width of no. 1. use d07 to d00 as general-purpose ports. (a12 to a00) (d15 to d08) p3dir= ***00000 p3md= 00011111 use a23 to a13 as general-purpose ports. 16bit p0dir to p2dir, p4dir and p0md to p2md, p4md are use a23 to a13 as general-purpose ports. (d15 to d00) same as those in the above 16-bit bus width of no. 1. p3dir and p3md are same as those in the above 8-bit bus width. 2-2 external memory connection examples 2-2-1 memory expansion mode (address/data separated mode) in this lsi series, the control registers for address or data setting need to be set as follows during address/data separated mode. [see chapter 8 ports.]
41 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface p0dir to p2dir, p4dir and p0md to p2md, p4md are no.8 up to 16k bytes 8bit same as those in the above 8-bit bus width of no. 1. use d07 to d00 as general-purpose ports. (a13 to a00) (d15 to d08) p3dir= **000000 p3md= 00111111 use a23 to a14 as general-purpose ports. 16bit p0dir to p2dir, p4dir and p0md to p2md, p4md are use a23 to a14 as general-purpose ports. (d15 to d00) same as those in the above 16-bit bus width of no. 1. p3dir and p3md are same as those in the above 8-bit b us w idth . p0dir to p2dir, p4dir and p0md to p2md, p4md are no.9 up to 32k bytes 8bit same as those in the above 8-bit bus width of no. 1. use d07 to d00 as general-purpose ports. (a14 to a00) (d15 to d08) p3dir= *0000000 p3md= 01111111 use a23 to a15 as general-purpose ports. p0dir to p2dir, p4dir and p0md to p2md, p4md are 16bit same as those in the above 16-bit bus width of no. 1. use a23 to a15 as general-purpose ports. (d15 to d00) p3dir and p3md are same as those in the above 8-bit bus width. p0dir to p2dir, p4dir and p0md to p2md, p4md are no.10 up to 64k bytes 8bit same as those in the above 8-bit bus width of no. 1. use d07 to d00 as general-purpose ports. (a15 to a00) (d15 to d08) p3dir= 00000000 p3md= 11111111 use a23 to a16 as general-purpose ports. p0dir to p2dir, p4dir and p0md to p2md, p4md are 16bit same as those in the above 16-bit bus width of no. 1. use a23 to a16 as general-purpose ports. (d15 to d00) p3dir and p3md are same as those in the above 8-bit bus width. p0dir to p3dir and p0md to p3md are same as those no.11 up to 128k bytes 8bit (all spaces) in the above 8-bit bus width of no. 10. use d07 to d00 as general-purpose ports. (a16 to a00) (d15 to d08) p4dir= *******0 p4md= 00000001 use a23 to a17 as general-purpose ports. p0dir to p3dir and p0md to p3md are same as those 16bit in the above 16-bit bus width of no. 10. use a23 to a17 as general-purpose ports. (d15 to d00) p4dir and p4md are same as those in the above 8-bit bus width. p0dir to p3dir and p0md to p3md are same as those no.12 up to 256k bytes 8bit (all spaces) in the above 8-bit bus width of no. 10. use d07 to d00 as general-purpose ports. (a17 to a00) (d15 to d08) p4dir= ******00 p4md= 00000011 use a23 to a18 as general-purpose ports. p0dir to p3dir and p0md to p3md are same as those 16bit in the above 16-bit bus width of no. 10. use a23 to a18 as general-purpose ports. (d15 to d00) p4dir and p4md are same as those in the above 8-bit bus width. p0dir to p3dir and p0md to p3md are same as those no.13 up to 512k bytes 8bit (all spaces) in the above 8-bit bus width of no. 10. use d07 to d00 as general-purpose ports. (a18 to a00) (d15 to d08) p4dir= *****000 p4md= 00000111 use a23 to a19 as general-purpose ports. p0dir to p3dir and p0md to p3md are same as those 16bit in the above 16-bit bus width of no. 10. use a23 to a19 as general-purpose ports. (d15 to d00) p4dir and p4md are same as those in the above 8-bit bus width. p0dir to p3dir and p0md to p3md are same as those no.14 up to 1m bytes 8bit (all spaces) in the above 8-bit bus width of no. 10. use d07 to d00 as general-purpose ports. (a18 to a00) (d15 to d08) p4dir= ****0000 p4md= 00001111 use a23 to a20 as general-purpose ports. p0dir to p3dir and p0md to p3md are same as those 16bit in the above 16-bit bus width of no. 10. use a23 to a20 as general-purpose ports. (d15 to d00) p4dir and p4md are same as those in the above 8-bit bus width. p0dir to p3dir and p0md to p3md are same as those no.15 up to 2m bytes 8bit (all spaces) in the above 8-bit bus width of no. 10. use d07 to d00 as general-purpose ports. (a19 to a00) (d15 to d08) p4dir= ***00000 p4md= 00011111 use a23 to a21 as general-purpose ports. p0dir to p3dir and p0md to p3md are same as those 16bit in the above 16-bit bus width of no. 10. use a23 to a21 as general-purpose ports. (d15 to d00) p4dir and p4md are same as those in the above 8-bit bus width. p0dir to p3dir and p0md to p3md are same as those no.16 up to 4m bytes 8bit (all spaces) in the above 8-bit bus width of no. 10. use d07 to d00 as general-purpose ports. (a20 to a00) (d15 to d08) p4dir= **000000 p4md= 00111111 use a23 to a22 as general-purpose ports. p0dir to p3dir and p0md to p3md are same as those 16bit in the above 16-bit bus width of no. 10. use a23 to a22 as general-purpose ports. (d15 to d00) p4dir and p4md are same as those in the above 8-bit bus width. p0dir to p3dir and p0md to p3md are same as those no.17 up to 8m bytes 8bit (all spaces) in the above 8-bit bus width of no. 10. use d07 to d00 as general-purpose ports. (a21 to a00) (d15 to d08) or p4dir= *0000000 p4md= 01111111 in addition, use a22 as a general-purpose (/cs2 to /cs0, port when the address is determined by a21 to a00) p6md= *0 - -*** - /cs2 to /cs0. p0dir to p3dir and p0md to p3md are same as those 16bit in the above 16-bit bus width of no. 10. use a23 as a general-purpose port. (d15 to d00) p4dir and p4md are same as those in the above 8-bit in addition, use a22 as a general-purpose bus width. port when the address is determined by /cs2 to /cs0. p0dir to p3dir and p0md to p3md are same as those no.18 up to 16m bytes 8bit (all spaces) in the above 8-bit bus width of no. 10. use d07 to d00 as general-purpose ports. (a23 to a00) (d15 to d08) or p4dir= 00000000 p4md= 11111111 in addition, use a23 to a22 as general- (/cs3 to /cs0, purpose ports when the address is a23 to a00) p6md= 00 - -*** - determined by /cs3 to cs0. p0dir to p3dir and p0md to p3md are same as those 16bit in the above 16-bit bus width of no. 10. use /cs3 to /cs0 as general-purpose ports. (d15 to d00) p4dir and p4md are same as those in the above 8-bit in addition, use a23 to a22 as general- bus width. purpose ports when the address is determined by /cs3 to cs0.
42 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 2-2-2 external memory connection examples (address/data separeted mode) this section describes the external memory connection examples. memory system with 16-bit bus width the following is the example of connecting the 4-mbit rom (256 kilowords a18-a00 d15-d00 weh wel cs0 cs1 re d15-d00 cs3 wait adsep word rom a17-a00 cs oe sram a16-a00 i/o7-0 we cs oe oe weh wel da asic wait cs 15:0 15:8 15:0 18:1 16:0 port a23-a19 figure 2-2-1 memory connection example with 16-bit bus width (address/data separated mode) 5 14 13 12 11 10 1 9876543210 1 t i a w0 t i a w 01 memmd0: x?0fc30 5 14 13 12 11 10 1 98 76543210 d o m b 1 t i a w0 t i a w 1 00 memmd1: x?0fc32 5 14 13 12 11 10 1 98 76543210 d o m b 1 t i a w0 t i a w 0 11 memmd3: x?0fc36
43 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface memory system with 8-bit bus width in all areas the following is the example of connecting the 4-mbit rom (512 kilowords a18-a00 d15-d08 a23-a19 weh cs0 cs1 re d15-d00 cs3 wait adsep word rom a18-a00 cs oe sram a16-a00 i/o7-0 we cs oe oe da asic wait cs 15:8 15:8 15:8 18:0 16:0 d07-d00 we port figure 2-2-2 memory connection example with 8-bit bus width (address/data separated mode) 5 14 13 12 11 10 1 9876543210 1 t i a w0 t i a w 10 memmd0: x?0fc30 5 14 13 12 11 10 1 98 76543210 d o m b 1 t i a w0 t i a w 1 01 memmd1: x?0fc32 5 14 13 12 11 10 1 98 76543210 d o m b 1 t i a w0 t i a w 1 11 memmd3: x?0fc36 in the mn10200 series, the data is input to the upper pins of d15 to d08.
44 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface rom, ram access timing with 16-bit bus width 8-bit write low side 8-bit write high side 16-bit write read osci sysclk a23-00 d15-08 d07-00 cs re weh wel (a00=h) (a00=l) ) figure 2-2-3 no wait access timing with 16-bit bus width 8-bit write low side 16-bit write read osci sysclk a23-00 d15-08 d07-00 cs re weh wel figure 2-2-4 1 wait access timing with 16-bit bus width
45 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 16-bit read osci sysclk a23-00 d15-08 d07-00 cs re weh wel wait 16-bit write figure 2-2-5 handshake access timing with 16-bit bus width osci sysclk a23-00 d15-08 cs re weh 16-bit read 8-bit write (a00=0) (a00=1) figure 2-2-6 no wait access timing with 8-bit bus width rom, ram access timing with 16-bit bus width rom, ram access timing with 8-bit bus width
46 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface rom, ram access timing with 8-bit bus width 8-bit write 16-bit read osci sysclk a23-00 d15-08 cs re weh (a00=0) (a00=1) figure 2-2-7 1 wait access timing with 8-bit bus width 16-bit write osci sysclk a23-00 d15-08 cs we wait figure 2-2-8 handshake access timing with 8-bit bus width
47 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface access timing during bus request (address/data separated mode) osco sysclk a23-16 d15-00 csn bre re weh,wel wait breq brack bus master d a d cpu cpu external device floating floating floating floating floating floating figure 2-2-9 access timing during bus request (address/data separated mode)
48 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface no.1 up to 64 kbytes 8/16bit p0dir= -------0 p0md= -------1 use a23 to a16 as general-purpose ports. p1dir= -------0 p1md= -------1 p4dir= *******0 p4md= 00000000 no.2 up to 128 kbytes 8/16bit p0dir to p1dir and p0md and p1md are set as same as use a23 to a17 as general-purpose ports. those in the above. p4dir= *******1 p4md= 00000001 no.3 up to 256 kbytes 8/16bit p0dir to p1dir and p0md and p1md are set as same as use a23 to a18 as general-purpose ports. those in the above. p4dir= ******11 p4md= 00000011 no.4 up to 512 kbytes 8/16bit p0dir to p1dir and p0md and p1md are set as same as use a23 to a19 as general-purpose ports. those in the above. p4dir= *****111 p4md= 00000111 no.5 up to 1 mbyte 8/16bit p0dir to p1dir and p0md and p1md are set as same as use a23 to a20 as general-purpose ports. those in the above. p4dir= ****1111 p4md= 00001111 no.6 up to 2 mbytes 8/16bit p0dir to p1dir and p0md and p1md are set as same as use a23 to a21 as general-purpose ports. those in the above. p4dir= ***11111 p4md= 00011111 no.7 up to 4 mbytes 8/16bit p0dir to p1dir and p0md and p1md are set as same as use a23 to a22 as general-purpose ports. those in the above. p4dir= **111111 p4md= 00111111 no.8 up to 8 mbytes 8/16bit p0dir to p1dir and p0md and p1md are set as same as use a23 as a general-purpose port. those in the above. p4dir= *1111111 p4md= 01111111 p6md= *0 - -*** - no.9 up to 16 mbytes 8/16bit p0dir to p1dir and p0md and p1md are set as same as those in the above. p4dir= 11111111 p4md= 11111111 p6md= 00 - -*** - 2-2-3 memory expansion mode (address/data shared mode) in this lsi series, the control registers for address or data setting need to be set as follows during address/data shared mode. [see chapter 8 ports.]
49 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface
50 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface 2-2-4 external memory connection examples (address/data shared mode) this section describes the external memory connection examples. memory system with 16-bit bus width the following is the example of connecting the 4-mbit rom (256 kilo words a18-a16 cs0 cs1 cs3 wait d15-d00 rom a17-a00 cs oe sram a16-a00 i/o7-0 cs oe da asic cs 18:1 ad07-a00 ad15-ad08 dq e dq e ale we oe wait 7:0 15:8 18:16 re weh wel 15:8 7:0 15:0 15:8 15:0 16:0 weh wel a23-a19 word port adsep figure 2-2-10 memory connection example with 16-bit bus width (address/data shared mode) 5 14 13 12 11 10 1 9876543210 1 t i a w0 t i a w 01 memmd0: x?0fc30 5 14 13 12 11 10 1 98 76543210 d o m b 1 t i a w0 t i a w 1 01 memmd1: x?0fc32 5 14 13 12 11 10 1 98 76543210 d o m b 1 t i a w0 t i a w 0 11 memmd3: x?0fc36 during the address/data shared mode, this lsi series operates in 1 wait cycle even though wait[1:0] are set to 00 .
51 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface memory system with 8-bit bus width in all areas the following is the example of connecting the 4-mbit rom (512 kilo words a18-a16 cs0 cs1 cs3 wait a18-a00 rom i/o7-0 cs oe sram a16-a00 i/o7-0 cs oe a asic cs 18:0 ad07-ad00 ad15-ad08 dq e ale we oe wait 7:0 15:8 18:16 we re weh d figure 2-2-11 memory connection example with 8-bit bus width (address/data shared mode) 5 14 13 12 11 10 1 9876543210 1 t i a w0 t i a w 10 memmd0: x?0fc30 5 14 13 12 11 10 1 98 76543210 d o m b 1 t i a w0 t i a w 1 01 memmd1: x?0fc32 5 14 13 12 11 10 1 98 76543210 d o m b 1 t i a w0 t i a w 1 11 memmd3: x?0fc36 in the mn10200 series, the data is input to the upper pins of d15 to d08.
52 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface rom, ram access timing with 16-bit bus width osci sysclk a23-a16 ad15-ad08 ad07-ad00 ale cs re weh wel read 16-bit write 8-bit write hi g h side 8-bit write low side (address) (address) (data) (data) (ad00=0) (address) (address) (ad00=0) (address) (address) (ad00=1) (address) (address) (ad00=0) (data) (data) (data) (data) figure 2-2-12 fixed wait access timing with 16-bit bus width osci sysclk a23-a16 ad15-ad08 ad07-ad00 ale cs re weh wel wait read write (address) (address) (data) (data) (address) (address) (data) (data) figure 2-2-13 handshake access timing with 16-bit bus width
53 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface rom, ram access timing with 8-bit bus width 16-bit read 8-bit write high side 8-bit write low side (address) (address) (data) (ad00=0) (address) (address) (ad00=1) (address) (address) (ad00=1) (address) (address) (ad00=0) (data) (data) (data) lower 8-bit access upper 8-bit access osci sysclk a23-a16 ad15-ad08 ad07-ad00 ale cs re weh wel figure 2-2-14 fixed wait access timing with 8-bit bus width osci sysclk a23-a16 ad15-ad08 ad07-ad00 16-bit write (address) (address) (address) (address) (data) (data) lower 8-bit access (ad00=0) (ad00=1) ale cs re weh wel wait upper 8-bit access figure 2-2-15 handshake access timing with 8-bit bus width
54 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 2 bus interface access timing during bus request (address/data shared mode) osco sysclk a23-a16 d15-d00 ale csn re weh,l wait breq brack bus master dd cpu cpu external device floating floating floating floating floating floating a a figure 2-2-16 access timing during bus request (address/data shared mode)
0 1 2 3 4 5 6 7 8 9 chapter 3 interrupts
56 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts 3-1 interrupts 3-1-1 overview the interrupt controller contains eight groups. each group has some inter- rupt vectors . when an interrupt occurs, the cpu receives an interrupt re- quest. [see the mn10200 series lsi users manual linear addressing version.] table 3-1-1 list of interrupt control registers p u o r g t p u r r e t n i r o t c e v t p u r r e t n i ) n o i t i s o p t i b n t d i s i r e b m u n ( r e t s i g e r l o r t n o c 0 p u o r g t p u r r e t n i n o i t c u r t s n i d e n i f e d n u 2 t p u r r e t n i r e m i t g o d h c t a w 1 t p u r r e t n i i m n 0 0 r e t s i g e r l o r t n o c t p u r r e t n i e l b a k s a m n o n ' 0 4 c f 0 0 ' x : r c i 0 g 1 p u o r g d e v r e s e r 3 w o l f r e d n u 5 r e t n u o c / r e m i t 2 w o l f r e d n u 0 r e t n u o c / r e m i t 1 0 q r i t p u r r e t n i l a n r e t x e 0 1 r e t s i g e r l o r t n o c t p u r r e t n i e l b a k s a m ' 2 4 c f 0 0 ' x : r c i 1 g 2 p u o r g d e v r e s e r 3 d n e n o i s r e v n o c d / a 2 w o l f r e d n u 1 r e t n u o c / r e m i t 1 1 q r i t p u r r e t n i l a n r e t x e 0 2 r e t s i g e r l o r t n o c t p u r r e t n i e l b a k s a m ' 4 4 c f 0 0 ' x : r c i 2 g 3 p u o r g d n e n o i t p e c e r 0 h c l a i r e s 3 d n e n o i s s i m s n a r t 0 h c l a i r e s 2 w o l f r e d n u 2 r e t n u o c / r e m i t 1 2 q r i t p u r r e t n i l a n r e t x e 0 3 r e t s i g e r l o r t n o c t p u r r e t n i e l b a k s a m ' 6 4 c f 0 0 ' x : r c i 3 g 4 p u o r g d n e n o i t p e c e r 1 h c l a i r e s 3 d n e n o i s s i m s n a r t 1 h c l a i r e s 2 w o l f r e d n u 3 r e t n u o c / r e m i t 1 3 q r i t p u r r e t n i l a n r e t x e 0 4 r e t s i g e r l o r t n o c t p u r r e t n i e l b a k s a m ' 8 4 c f 0 0 ' x : r c i 4 g 5 p u o r g e l b a n e g n i d n o p s e r r o c e h t t e s ( d e v r e s e r 3 ) . 0 o t g a l f e l b a n e g n i d n o p s e r r o c e h t t e s ( d e v r e s e r 2 ) . 0 o t g a l f w o l f r e d n u 4 r e t n u o c / r e m i t 1 4 q r i t p u r r e t n i l a n r e t x e 0 5 r e t s i g e r l o r t n o c t p u r r e t n i e l b a k s a m ' a 4 c f 0 0 ' x : r c i 5 g 6 p u o r g d n e c t a 3 b e r u t p a c / e r a p m o c 6 r e t n u o c / r e m i t 2 a e r u t p a c / e r a p m o c 6 r e t n u o c / r e m i t 1 w o l f r e d n u 6 r e t n u o c / r e m i t 0 6 r e t s i g e r l o r t n o c t p u r r e t n i e l b a k s a m ' c 4 c f 0 0 ' x : r c i 6 g 7 p u o r g d e v r e s e r 3 b e r u t p a c / e r a p m o c 7 r e t n u o c / r e m i t 2 a e r u t p a c / e r a p m o c 7 r e t n u o c / r e m i t 1 w o l f r e d n u 7 r e t n u o c / r e m i t 0 7 r e t s i g e r l o r t n o c t p u r r e t n i e l b a k s a m ' e 4 c f 0 0 ' x : r c i 7 g
57 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts the control register is assigned to its corresponding interrupt group except group 0 and controls the assigned interrupt vectors. for example, in the mn102l(f, p) 25x, when timer 0 underflows, the interrupt request flag (irf1=tm0ir) of the maskable interrupt control register (g1icr) becomes 1. at this point, the cpu receives an interrupt request if the corresponding interrupt enable flag (ien1=tm0ie) is 1. comparing the interrupt mask level (im2 - 0 ) of the processor status word (psw) and the group interrupt level (ilvn=g1lv[2:0]) of the g1icr register determines whether the cpu receives the inter- rupt or not. 15 14 13 12 11 10 9 7 6 4 3 2 1 0 8 5 tm0 id irq0 id g1 lv2 g1 lv1 g1 lv0 tm5 id tm0 ir irq0 ir tm5 ir tm0 ie irq0 ie tm5 ie group interrupt level ilvn interrupt level setup interrupt enable flag ienn interrupt enable setup interrupt request flag irfn interrupt vector generation interrupt detect flag idtn interrupt request detect g1icr: x?0fc42 see 2-5 interrupt controller in the mn10200 series lsi user s manual linear ad- dressing version for detail operations. see the mn10200 series instruction manual lin- ear addressing version for interrupt service flow and handler programming. set the interrupt enable flags ien[3:2] (bits [11:10]) of the g5icr to 0.
58 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts 3-2 external interrupts 3-2-1 external pin interrupts group 5 to group 1 control external pin interrupts. the extmd register sets the interrupt conditions. the extmd register sets the inter- rupt levels and timing of external interrupts. the extmd register specifies each pins s level or edge. 15 14 13 12 11 10 9 7 6 4 3 2 1 0 8 5 irq0 tg1 irq0 tg0 irq0 tg0 irq2 tg1 irq2 tg0 irq3 tg0 irq4 tg1 irq4 tg0 eirq0 irq3 tg1 irq1 tg1 eirq1 eirq2 eirq3 eirq4 00: an interrupt occurs at low level 01: an interrupt occurs at high level 10: an interrupt occurs at negative edge 11: an interrupt occurs at pogitive edge extmd: x?0fc50 3-2-2 nmi interrupts this series supports a nmi interrupt. the nmi interrupt occurs on the negative edge of nmi pin. an nmi interrupt occurs when the cpu is in the bus release state or the handshake access is in wait state.
59 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts
60 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts 3-3 interrupt setup examples 3-3-1 external pin interrupt setup an interrupt occurs on the negative edge from the external interrupt pin irq0 (pa0). the external interrupt edge specification register (extmd) sets the interrupt request at low level after reset release, and the irq0ir bit of the maskable interrupt control register 1 (g1icr) becomes 0. interrupt enable setup (1) set the interrupt conditions of the interrupt pin irq0 (pa0). set the irq0tg of the extmd register to 2. (bit setting: 10) 5 14 13 12 11 10 1 9876543210 4 q r i 1 g t 4 q r i 0 g t 3 q r i 1 g t 3 q r i 0 g t 2 q r i 1 g t 2 q r i 0 g t 1 q r i 1 g t 1 q r i 0 g t 0 q r i 1 g t 0 q r i 0 g t 0000000010 extmd: x?0fc50 (2) enable interrupts. at this point, clear all prior interrupt requests. to do this, set g1lv[2:0], irq0ir and irq0ie of the g1icr register to an interrupt level, 0 and 1, respectively. 5 14 13 12 11 10 1 9876543210 1 g 2 v l 1 g 1 v l 1 g 0 v l 5 m t e i 0 m t e i 0 q r i e i 5 m t r i 0 m t r i 0 q r i r i 5 m t d i 0 m t d i 0 q r i d i 100 001 000 000 g1icr: x?0fc42 (3) enable interrupts by setting the interrupt enable flag (ie) of the processor status word (psw) to 1 and the interrupt mask level (imn) to 7 (bit setting:111). in this example, the interrupt level is 4.
61 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts thereafter, an interrupt occurs on the negative edge of the interrupt pin irq0 (pa0). the program branches to x 080008 when the interrupt accepted. interrupt service routine (4) specify the interrupt group by reading the interrupt accept group register (iagr) during interrupt preprocessing. (5) specify the interrupt vector in the group by reading the g1icr register. check the irq0id with the bit test instruction (btst). if irq0id is 1, execute the interrupt service routine. (6) clear the irq0ir bit of the g1icr register. (7) return to the main program with the interrupt return instruction (rti) after the interrupt service routine ends. pa0(irq0) extmd irq0ie irq0ir interrupt service routine registers [r/w] extmd(w) g1icr(r/w) low level negative edge (1) ( 2 )( 3 )( 4 )( 5 )( 6 )( 7 ) procedure g1icr(r/w) g1icr(r) ( 4 )( 5 )( 6 )( 7 ) normally, the program generates the interrupt start address and branches to that address. during interrupt service routine, the im and ie of psw become the inter- rupt level and 0 respectively. the multiple interrupts are not allowed. it means that other interrupts except the nonmaskable interrupt are not accepted during interrupt service rou- tine unless the psw is set. figure 3-3-1 external pin interrupt timing
62 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts 3-3-2 watchdog timer interrupt an interrupt occurs by using the watchdog timer. set the wdrst flag of the cpu mode control register (cpum) to enable ( 0 ) after reset. this starts the watchdog timer. a nonmaskable interrupt occurs when the watchdog counter overflows. because of this, the watchdog timer needs to be cleared during the main program. interrupt enable setup (1) enable interrupts by setting the interrupt enable flag (ie) of the processor status word (psw) to 1 and the interrupt mask level (imn) to 7 (bit setting:111). (2) clear the wdrst flag of the cpum register. this starts the watchdog timer. 5 14 13 12 11 10 1 9876543210 d w t s r c s o d i p o t st l a h1 c s o0 c s o 0 00000 cpum: x?0fc00 watchdog timer clear (3) set the wdrst flag of the cpum register to 1 and then immediately clear to 0. the watchdog timer clears to 0 when the wdrst flag is 1. interrupt service routine the program branches to x 080008 when an interrupt is generated and accepted. (4) specify the interrupt group by reading the interrupt accept group register (iagr) during interrupt preprocessing. (5) verify a watchdog interrupt by reading the nonmaskable interrupt control register (g0icr). check the wdif with the bit test instruction (btst). if wdif is 1, execute the interrupt service routine. when the watchdog timer counts 65536 cycles of sysclk (6.5536 ms with a 20-mhz oscillator), a watchdog interrupt occurs. normally, clear the watchdog timer before an interrypt occurs. normally, the program generates the interrupt start address and branches to that address. the im of psw becomes the high- est level during interrupt service rou- tine and other interrupts are not ac- cepted.
63 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts (6) clear the wdir flag of the g0icr register. (7) return to the main program with the interrupt return instruction (rti) after the interrupt service routine ends. the watchdog timer and the oscillation stabilization wait counter are shared. the watch- dog timer functions as the oscillation stabilization wait counter when the cpu returns from the stop mode. because of this, the wdif flag is cleared to 0 when the cpu move to the stop mode. the wdif flag cleared to 0 again after the cpu moves to the normal mode. [see 2-6 standby function in the mn10200 series lsi user s manual linear addressing version.] rst pin wd count wdrst(cpum) wdif(g0icr) interrupt service routine cpum(w) cpum(w) cpum(w) g0icr(r/w) (1) (2) (4)(5)(6)(7) (3) (3) clear overflow registers [r/w] procedure figure 3-3-2 watchdog interrupt timing the watchdog interrupt does not occur when the chip is in bus release. the watchdog interrupt occurs when the chip waits for the handshake access. when a watchdog interrupt is ac- cepted during wait for the handshake access, the watchdog interrupt oc- curs by suspending the bus cycle during the wait state. therefore, the bus cycle operation is not guaranteed when the watchdog interrupt occurs during the wait.
64 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 3 interrupts
0 1 2 3 4 5 6 7 8 9 chapter 4 timers
66 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-1 timers 4-1-1 overview this lsi series contains six 8-bit timers (timer 0 to timer 5) and two 16-bit timers (timer 6 and timer 7). table 4-1-1 timer function (1/2) group 1 (g1icr) ?tm0ir timer 0 underflow ?tm0io pin ? /128(*1) ? (*2) ? fxi/4(*3) down counting ? ? ? interrupt request destination interrupt source clock source group 2 (g2icr) ?tm1ir timer 1 underflow ?tm1io pin ? fxi/4 ? timer 0 ? down counting ? ? ? ? group 3 (g3icr) ?tm2ir timer 2 underflow ?tm2io pin ? timer 1 ? timer 0 ? down counting ? ? ? ? group 4 (g4icr) ?tm3ir timer 3 underflow ?tm3io pin ? timer 2 ? timer 0 ? down counting ? ? ? ? timer 0 8-bit timer counting method interval timer event counter timer output pwm two-phase timer output one-shot pulse output one-phase capture input two-phase capture input two-phase encoder external count direction control external count reset control serial interface transfer clock generation a/d conversion timing generation timer 1 timer 2 timer 3 function timer
67 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers table 4-1-1 timer function (2/2) group 5 (g5icr) ?tm4ir timer 4 underflow ?tm4io pin ? timer 3 ? timer 0 ? fxi/4 down counting ? ? ? interrupt request destination interrupt source clock source group 1 (g1icr) ?tm5ir timer 5 underflow ?tm5io pin ? timer 4 ? timer 0 ? fxi/4 down counting ? ? ? group 6 (g6icr) ?tm6uir ?tm6air ?tm6bir timer 6 underflow timer 6 compare a or capture a match timer 6 compare b or capture b match ?sysclk ? timer 4 ? timer 5 ? tm6iob pin ?two-phase encoder up/down counting ? ? ? arbitrary duty ? ? ? ? 4x, 1x ? ? group 7 (g7icr) ?tm7uir ?tm7air ?tm7bir timer 7 underflow timer 7 compare a or capture a match timer 7 compare b or capture b match ?sysclk ? timer 4 ? timer 5 ? tm7iob pin ?two-phase encoder up/down counting ? ? ? arbitrary duty ? ? ? ? 4x, 1x ? ? timer 4 8-bit timer counting method interval timer event counter timer output pwm two-phase timer output one-shot pulse output one-phase capture input two-phase capture input two-phase encoder external count direction control external count reset control serial interface transfer clock generation a/d conversion timing generation timer 5 timer 6 timer 7 function timer *1 system clock (10 mhz with a 20-mhz ocillator)/128 *2 system clock (10 mhz with a 20-mhz ocillator) *3 low-speed clock (32 khz)/4
68 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers tmnbr value tmnio (input) tmnbc value time tmnbr value tmnio (output) tmnbc value time interrupts tmnca tmnioa (output) tmnbc value time tmncb figure 4-1-3 pwm output timing (timer 6 and timer 7) figure 4-1-2 timer output, interval timer timing (timer 0 to timer 5) figure 4-1-1 event counter timing (timer 0 to timer 5)
69 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers tmnca tmnioa (output) tmnbc value time tmncb rewrite the tmncb value keep in the current cycle reflect the result from the next cycle figure 4-1-4 pwm output timing (data write) (timer 6 and timer 7) tmnca tmnbc value time tmncb tmnob (output) tmnoa (output) figure 4-1-5 two-phase timer output timing (timer 6 and timer 7) tmnca tmnoa (output) tmnbc value time tmnib (input) figure 4-1-6 one-shot pulse output timing (timer6 and timer 7)
70 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 0033 (example) 5a87(example) ffff tmnca (register value) tmnbc value time tmnib (input) tmnia (input) tmncb (register value) figure 4-1-7 one-phase capture input timing (timer6 and timer 7) 0033(example) 5a87(example) ffff tmnca tmnbc value time tmnib (input) tmnia (input) tmncb figure 4-1-8 two-phase capture input timing (timer 6 and timer 7) tmnib (input) tmnbc value time tmnia (input) figure 4-1-9 two-phase encoder (4x) timing
71 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers tmnib (input) tmnbc value time tmnia (input) figure 4-1-10 two-phase encoder (1x) timing (timer 6 and timer 7) tmnib (input) tmnbc value time tmnia (input) figure 4-1-11 external count direction control timing (timer 6 and timer 7) tmnia tmnbc value time tmnib (input) tmnca tmnic (input) figure 4-1-12 external count reset control (two-phase encoder) timing (timer 6 and timer 7)
72 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers timer 0 to timer 5 timer 0 to timer 5 are 8-bit timers. they are down counting and are divided by the 8-bit value set in the base register (tmnbr) plus one. (do not set 0 to tmnbr). an interrupt occurs when each timer underflows (the binary counter changes from x?0?to the 8-bit value). they can function as interval timers, event counters, clock output, base clock for serial interface and a/d conversion start timing. timer 6 and timer 7 timer 6 and timer 7 are 16-bit timers. they are up/down counting. each timer has two compare/capture registers (tmnca and tmncb). these registers capture and compare the up/down counter value, generate pwm and interrupts. the pwm contains the double buffer mode that changes the cycle and transition from the next cycle. this prevents the pwm waveform losses and distorts during timing changes. these timers can function as interval timers, event counters (at clock oscillation), one-phase pwm, two-phase pwm, two capture input, dual two-phase encoders, one-shot pulse generators and external count direction controllers. timer 1 to timer 5 can cascade. for example, cascading timer 1 and timer 2 can form as a 16-bit timer. cascading timer 3, timer 4 and timer 5 can form as a 24-bit timer. cas- cading these timers can form a 40- bit timer at most. an underflow interrupt occurs only when these timers are down count- ing.
73 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers figure 4-1-13 shows the timer configuration. combining timers serves as various interval timers. figure 4-1-13 timer configuration sysclk (10 mhz) clock synchronous serial timer output long-term interval timer clock 8-bit timer timer 0 (divided by 2 to 256) 8-bit timer timer 2 (divided by 2 to 256) 8-bit timer timer 1 (divided by 2 to 256) 16-bit timer timer 3 timer 4 (divided by 2 to 65536) 8-bit timer timer 5 (divided by 2 to 256) fxi/4 (8 khz) each timer n (n=2 to 5) cascade inputs cascade output of timer n-1. therefore, timer does not function as a 8-bit counter but it functions as a 16-bit counter. sysclk is a signal of dividing the clock from osci pin by 2 (10 mhz with a 20-mhz oscillator) during normal mode or halt0 mode. sysclk becomes a signal of dividing the clock from xi pin by 2 (16 khz with a 32-khz oscillator) during slow mode or halt1 mode. sysclk stops during stop0 mode or stop1 mode. sysclk outputs to the external sysclk pin. the fxi/4 means a signal of dividing the clock from xi pin by 4 (18 khz with a 32- khz oscillator) during modes except stop0 and stop1 modes. the fxi/4 stops during stop0 or stop1 mode.
74 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-1-2 control registers the following table shows timer control registers. r e t s i g e rs s e r d d aw / rn o i t c n u f 0 r e m i t d m 0 m t c b 0 m t r b 0 m t ' 0 2 e f 0 0 ' x ' 0 0 e f 0 0 ' x ' 0 1 e f 0 0 ' x w / r r w / r r e t s i g e r e d o m 0 r e m i t r e t n u o c y r a n i b 0 r e m i t r e t s i g e r e s a b 0 r e m i t 1 r e m i t d m 1 m t c b 1 m t r b 1 m t ' 1 2 e f 0 0 ' x ' 1 0 e f 0 0 ' x ' 1 1 e f 0 0 ' x w / r r w / r r e t s i g e r e d o m 1 r e m i t r e t n u o c y r a n i b 1 r e m i t r e t s i g e r e s a b 1 r e m i t 2 r e m i t d m 2 m t c b 2 m t r b 2 m t ' 2 2 e f 0 0 ' x ' 2 0 e f 0 0 ' x ' 2 1 e f 0 0 ' x w / r r w / r r e t s i g e r e d o m 2 r e m i t r e t n u o c y r a n i b 2 r e m i t r e t s i g e r e s a b 2 r e m i t 3 r e m i t d m 3 m t c b 3 m t r b 3 m t ' 3 2 e f 0 0 ' x ' 3 0 e f 0 0 ' x ' 3 1 e f 0 0 ' x w / r r w / r r e t s i g e r e d o m 3 r e m i t r e t n u o c y r a n i b 3 r e m i t r e t s i g e r e s a b 3 r e m i t 4 r e m i t d m 4 m t c b 4 m t r b 4 m t ' 4 2 e f 0 0 ' x ' 4 0 e f 0 0 ' x ' 4 1 e f 0 0 ' x w / r r w / r r e t s i g e r e d o m 4 r e m i t r e t n u o c y r a n i b 4 r e m i t r e t s i g e r e s a b 4 r e m i t 5 r e m i t d m 5 m t c b 5 m t r b 5 m t ' 5 2 e f 0 0 ' x ' 5 0 e f 0 0 ' x ' 5 1 e f 0 0 ' x w / r r w / r r e t s i g e r e d o m 5 r e m i t r e t n u o c y r a n i b 5 r e m i t r e t s i g e r e s a b 5 r e m i t 6 r e m i t d m 6 m t c b 6 m t a c 6 m t x a c 6 m t b c 6 m t x b c 6 m t ' 0 3 e f 0 0 ' x ' 2 3 e f 0 0 ' x ' 4 3 e f 0 0 ' x ' 6 3 e f 0 0 ' x ' 8 3 e f 0 0 ' x ' a 3 e f 0 0 ' x w / r r w / r - w / r - r e t s i g e r e d o m 6 r e m i t r e t n u o c y r a n i b 6 r e m i t a r e t s i g e r e r u t p a c / e r a p m o c 6 r e m i t a t e s r e t s i g e r e r u t p a c / e r a p m o c 6 r e m i t b r e t s i g e r e r u t p a c / e r a p m o c 6 r e m i t b t e s r e t s i g e r e r u t p a c / e r a p m o c 6 r e m i t 7 r e m i t d m 7 m t c b 7 m t a c 7 m t x a c 7 m t b c 7 m t x b c 7 m t ' 0 4 e f 0 0 ' x ' 2 4 e f 0 0 ' x ' 4 4 e f 0 0 ' x ' 6 4 e f 0 0 ' x ' 8 4 e f 0 0 ' x ' a 4 e f 0 0 ' x w / r r w / r - w / r - r e t s i g e r e d o m 7 r e m i t r e t n u o c y r a n i b 7 r e m i t a r e t s i g e r e r u t p a c / e r a p m o c 7 r e m i t a t e s r e t s i g e r e r u t p a c / e r a p m o c 7 r e m i t b r e t s i g e r e r u t p a c / e r a p m o c 7 r e m i t b t e s r e t s i g e r e r u t p a c / e r a p m o c 7 r e m i t table 4-1-2 list of timer control registers the tm6cax register, the tm6cbx register, the tm7cax register and the tm7cbx register are dummy registers to specify the double buffer mode when the pwm is output.
75 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-1-3 timer block diagram this section describes block diagrams of timer 0 to timer 7. (x'00fe10') (x'00fe00') tm0md (x'00fe20') clock source for timer1 to timer 5 tm0io pin tm0io pin sysclk selector 0 1 2 3 interrupt controller 1/2 reset underflow reload timer 0 base register tm0br tm0ld tm0en tm0s0 tm0s1 load count 8 timer 0 binary counter tm0bc 8 8 8 data bus sysclk/128 low-speed clock/4 figure 4-1-14 timer 0 block diagram (x'00fe11') (x'00fe01') tm1md (x'00fe21') timer 1 cascade signal tm1io pin a/d conversion controller tm1io pin selector 0 1 2 3 interrupt controller 1/2 reset underflow reload timer 1 base register tm1br tm1ld tm1en tm1s0 tm1s1 load count 8 timer 1 binary counter tm1bc 8 8 8 data bus low-speed clock/4 timer 0 sysclk figure 4-1-15 timer 1 block diagram
76 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (x'00fe12') (x'00fe02') tm2md (x'00fe22') timer 2 cascade signal tm2io pin tm2io pin timer 1 cascade timer 0 sysclk selector 0 1 2 3 interrupt controller 1/2 reset underflow reload timer 2 base register tm2br tm2ld tm2en tm2s0 tm2s1 load count 8 timer 2 binary counter tm2bc 8 8 8 data bus serial i/f controller figure 4-1-16 timer 2 block diagram (x'00fe13') (x'00fe03') tm3md (x'00fe23') timer 3 cascade signal tm3io pin tm3io pin timer 2 cascade timer 0 sysclk selector 0 1 2 3 interrupt controller 1/2 reset underflow reload timer 3 base register tm3br tm3ld tm3en tm3s0 tm3s1 load count 8 timer 3 binary counter tm3bc 8 8 8 data bus serial i/f controller figure 4-1-17 timer 3 block diagram
77 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (x'00fe14') (x'00fe04') tm4md (x'00fe24') timer 4 cascade signal tm4io pin tm4io pin timer 3 cascade timer 0 selector 0 1 2 3 interrupt controller 1/2 reset underflow reload timer 4 base register tm4br tm4ld tm4en tm4s0 tm4s1 load count timer 4 binary counter tm4bc 8 8 8 data bus low-speed clock/4 figure 4-1-18 timer 4 block diagram data bus 8 8 (x'00fe15') (x'00fe05') tm5md (x'00fe25') tm5io pin (p30) timer 4 cascade timer 0 selector 0 1 2 3 interrupt controller underflow reload timer 5 base register tm5br tm5ld tm5en tm5s0 tm5s1 load count 8 timer 5 binary counter tm5bc 8 tm5io pin (p30) 1/2 reset low-speed clock/4 figure 4-1-19 timer 5 block diagram
78 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers clear [eclr] [lp] [en] [s] [ud] tm6ic timer 4 timer 5 sysclk tm6iob tm6ioa capture match [md] [nld] (when tm6bc=0) load tm6ioa tm6iob [tge] [one] u/d control tm6bc(x'00fe32') tm6cax (x'00fe36') tm6ca(x'00fe34') q r t q r s r q r t tm6cb(x'00fe38') tm6cbx (x'00fe3a') capture tm6md(x'00fe30') control [asel] selector selector figure 4-1-20 timer 6 block diagram clear [eclr] [lp] [en] [s] [ud] tm7ic timer 4 timer 5 sysclk tm7iob tm7ioa capture match [md] [nld] tm7ioa tm7iob [tge] [one] u/d control tm7bc(x'00fe42') tm7cax (x'00fe46') tm7ca(x'00fe44') q r t q r s r q r t tm7cb(x'00fe48') tm7cbx (x'00fe4a') capture tm7md (x'00fe40') [asel] (when tm7bc=0) load control selector selector figure 4-1-21 timer 7 block diagram
79 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers
80 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-2 8-bit timer setup examples 4-2-1 event counter using 8-bit timer the event counter setup procedures for timer 0 to timer 5 are the same. in this example, timer 2 counts the rising edge of the tm2io pin input four times and generates an interrupt at underflow. (1) set the interrupt enable flag (ie) of the processor status word (psw) to 1. (2) verify that counting is stopped using the timer 2 mode register (tm2md). 76543210 2 m t n e 2 m t d l 2 m t s1 2 m t s0 0 0 0 0 tm2md: x?0fe22 (3) enable interrupts. at the same time, clear all prior interrupt requests. set g3lv[2:0] bits of the maskable interrupt control register 3 (g3icr) to the interrupt level of 6 to 0, tm2ir and tm2ie to 0 and 1, respectively. for example, write x?200 to the g3icr register. thereafter, an interrupt occurs when timer 2 underflows. 5 14 13 12 11 10 1 9876543210 3 g 2 v l 3 g 1 v l 3 g 0 v l r 0 c s e i t 0 c s e i 2 m t e i 2 q r i e i r 0 c s r i t 0 c s r i 2 m t r i 2 q r i r i r 0 c s d i t 0 c s d i 2 m t d i 2 q r i d i 100001000000000 g3icr: x?0fc46 this verification is unnecessary im- mediately after a reset.
81 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (4) set the timer divisor. since timer 2 divides the tm2io pin by 4, set the timer 2 base register (tm2br) to 3. (the valid range for tm2br is 1 to 255.) 76543210 2 m t 7 r b 2 m t 6 r b 2 m t 5 r b 2 m t 4 r b 2 m t 3 r b 2 m t 2 r b 2 m t 1 r b 2 m t 0 r b 00000011 tm2br: x?0fe12 (5) load the tm2br value to the tm2bc register. to do this, set tm2ld and tm2en of the tm2md register to 1 and 0 respectively. at the same time, select the clock source. set tm2s[1:0] to 00. (6) set both tm2ld and tm2en of the tm2md register to 0. if this setting is omitted, the timer 2 binary counter may not start at the first cycle. (7) set both tm2ld and tm2en to 0. this starts timer 2. counting starts at the beginning of the next cycle. when the timer 2 binary counter value reaches 0 and loads the value of 3 from the timer 2 base register (tm2br), a timer 2 underflow interrupt request occurs. interrupt enable tm2br tm2bc timer 2 tm2io g3icr(w) tm2br(w) (2) (4) (5) tm2md(w) tm2md(w) tm2md(w) (3) (6) (7) underflow interrupt 00 03 00 03 02 01 00 03 procedure tm2md(w) figure 4-2-1 event counter timing changing the clock source while controlling count operation will cor- rupt the binary counter value.
82 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers timer 0 setup (1) verify that timer 0 counting is stopped using the timer 0 mode register (tm0md). if setting 1 of divisor, write the dummy value (for example, x 0f ) once. 4-2-2 clock output using 8-bit timer timer 0 to timer 5 contain clock output functions. the setup procedures for timer 0 to timer 5 are same. in this example, timer 0 and timer 1 output 12 clock cycles (sysclk/6). sysclk (10 mhz) clock output 8-bit timer timer 1 8-bit timer timer 0 (divided by 2) (divided by 3) figure 4-2-2 clock output configuration (1) 76543210 m t0 n e m t0 d l m t0 s1 m t0 s0 01 10 tm0md: x?0fe20 (2) set the timer 0 divisor. since timer 0 divides sysclk by 2, set the timer 0 base register (tm0br) to 1. (the valid range for tm0br is 1 to 255.) 76543210 0 m t 7 r b m t0 6 r b m t0 5 r b m t0 4 r b m t0 3 r b m t0 2 r b m t0 1 r b m t0 0 r b 00000001 tm0br: x?0fe10 (3) load the tm0br value to tm0bc. to do this, set tm0ld and tm0en to 1 and 0 resepctively. 76543210 m t0 n e m t0 d l m t0 s1 m t0 s0 01 10 tm0md: x?0fe20 this verification is unnecessary im- mediately after a reset.
83 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (4) set both tm0ld and tm0en of the tm0md register to 0. if this setting is omitted, the timer 0 binary counter may not start at the first cycle. (5) set tm0ld and tm0en to 0 and 1 respectively. this starts timer 0. counting starts at the beginning of the next cycle. when the timer 0 binary counter value reaches 0 and loads the value of 1 from the timer 0 base register (tm0br), a timer 0 underflow interrupt request occurs. pin setup (6) select the tm1io pin to output using the port 8 i/o control register (p8dir) and the port 8 output mode register (p8md). (the set value is 2.) 76543210 8 p 7 r i d 8 p 6 r i d 8 p 5 r i d 8 p 4 r i d 8 p 3 r i d 8 p 2 r i d 8 p 1 r i d 8 p 0 r i d 00000010 76543210 8 p 7 d m 8 p 6 d m 8 p 5 d m 8 p 4 d m 8 p 3 d m 8 p 2 d m 8 p 1 d m 8 p 0 d m 00000010 p8dir: x?0ffe8 p8md: x?0fff8 timer 1 setup (7) verify that timer 1 counting is stopped using the timer 1 mode register (tm1md). 76543210 1 m t n e 1 m t d l m t1 s1 m t1 s0 00 10 tm1md: x?0fe21 (8) set the timer 1 divisor. since timer 1 divides timer 0 output by 3, set the timer 1 base register (tm1br) to 2. (the valid range for tm0br is 1 to 255.) 76543210 1 m t 7 r b m t1 6 r b m t1 5 r b m t1 4 r b m t1 3 r b m t1 2 r b m t1 1 r b m t1 0 r b 00000010 tm1br: x?0fe11 (9) load the tm1br value to tm1bc. to do this, set tm1ld and tm1en to 1 and 0 resepctively. at the same time, select the clock source. this verification is unnecessary im- mediately after a reset. if selecting 1 of divisor, set 0 to the timer 0 base register (tm0br) once again after step (5). the first count is the value set in step (2), but the second count becomes 1. for ex- ample, if 0 is set to tm0br in step (2), the first count is 257 and the sec- ond count becomes 1. changing the clock source while controlling count operation will cor- rupt the binary counter value.
84 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (10) set both tm1ld and tm1en of the tm1md register to 0. if this setting is omitted, the timer 0 binary counter may not start at the first cycle. (11) set tm1ld and tm1en to 0 and 1 respectively. this starts timer 1. counting starts at the beginning of the next cycle. when the tm1bc value reaches 0, tm1io output is inverted as soon as the value of 2 from the timer 1 base register (tm1br) is loaded. immediately after tm1bc starts counting, the tm1io output pin outputs 0. the tm1io output pin outputs 1 at the begin- ning of the next cycle when tm1bc becomes 0. then the tm1io output pin outputs 0 again at the beginning of the next cycle. this repeated operation results in 12 clock cycles. (1) (3) (4) (2) sysclk tm0br tm0bc tm0 output tm1br tm1bc tm1io output procedure 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 02 (5) (7) (8) (9) (10)(11) 00 02 01 00 02 01 00 02 (6) figure 4-2-3 clock output timing
85 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-2-3 interval timer using 8-bit timer the interval timer setup procedures for timer 0 to timer 5 are same. in this example, timer 0, timer 2 and timer 3 generate an interrupt at regular inter- vals (1 second). (to divide sysclk by 10,000,000, timer 0 divides sysclk by 250 and timer 2 and timer 3 divide sysclk by 40,000.) sysclk (10 mhz) interrupt request 8-bit timer timer 0 (divided by 250) 16-bit timer timer 3 timer 2 (divided by 40000) figure 4-2-4 clock output configuration (2) (1) set the interrupt enable flag (ie) of the processor status word (psw) to 1. (2) enable interrupts. at the same time, clear all prior interrupt requests. set g4lv[2:0] bits of the maskable interrupt control register 4 (g4icr) to the interrupt level of 6 to 0, tm3ir and tm3ie to 0 and 1, respectively. for example, write x 4200 to the g4icr register. thereafter, an interrupt occurs when timer 3 underflows. 5 14 13 12 11 10 1 9876543210 4 g 2 v l 4 g 1 v l 4 g 0 v l r 1 c s e i t 1 c s e i 3 m t e i 3 q r i e i r 1 c s r i t 1 c s r i 3 m t r i 3 q r i r i r 1 c s d i t 1 c s d i 3 m t d i 3 q r i d i 100001000000000 g4icr: x?0fc48 timer 0 setup (3) verify that timer 0 counting is stopped using the timer 0 mode register (tm0md). 76543210 m t0 n e m t0 d l m t0 s1 m t0 s0 00 10 tm0md: x?0fe20 (2) set the timer 0 divisor. since timer 0 divides sysclk by 250, set the timer 0 base register (tm0br) to 249. (the valid range for tm0br is 1 to 255.) 76543210 0 m t 7 r b m t0 6 r b m t0 5 r b m t0 4 r b m t0 3 r b m t0 2 r b m t0 1 r b m t0 0 r b 11111001 tm0br: x?0fe10 this verification is unnecessary im- mediately after a reset. if setting 1 of divisor, write the dummy value (for example, x 0f ) once.
86 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (5) load the tm0br value to tm0bc. to do this, set tm0ld and tm0en to 1 and 0 resepctively. 76543210 m t0 n e m t0 d l m t0 s1 m t0 s0 00 10 tm0md: x?0fe20 (6) set both tm0ld and tm0en of the tm0md register to 0. if this setting is omitted, the timer 0 binary counter may not start at the first cycle. (7) set tm0ld and tm0en to 0 and 1 respectively. this starts timer 0. counting starts at the beginning of the next cycle. when the timer 0 binary counter (tm0bc) reaches 0 and loads the value of 1 from the timer 0 base register (tm0br), a timer 0 underflow interrupt request occurs. timer 2 and timer 3 setup (8) verify that counting is stopped using the timer 2 mode register (tm2md) and the timer 3 mode register (tm3md). 76543210 2 m t n e 2 m t d l 2 m t s1 2 m t s0 00 00 tm2md: x?0fe22 (9) set the timer divisor. since the divisor is 40000 (x 9c40 ), set the timer 2 base register (tm2br) and the timer 3 base register (tm3br) to x 3f and x 9c . (the valid range is 1 to 255.) 76543210 2 m t 7 r b 2 m t 6 r b 2 m t 5 r b 2 m t 4 r b 2 m t 3 r b 2 m t 2 r b 2 m t 1 r b 2 m t 0 r b 00111111 tm2br: x?0fe12 76543210 3 m t n e 3 m t d l m t3 s1 3 m t s0 00 01 tm3md: x?0fe23 76543210 3 m t 7 r b m t3 6 r b m t3 5 r b m t3 4 r b m t3 3 r b m t3 2 r b m t3 1 r b m t3 0 r b 10011100 tm3br: x?0fe13 (10) load the tm2br value to tm2bc and the tm3br to tm3bc. to do this, set both tm2ld and tm3ld to 1, and both tm2en and tm3en to 0. at the same time, select the clock sources. (select timer 0 for the timer 2 clock source and timer 2 cascade for the timer 3 clock source.) if selecting 1 of divisor, set 0 to the timer 0 base register (tm0br) once again after step (7). the first count is the value set in step (4), but the second count becomes 1. for ex- ample, if 0 is set to tm0br in step (4), the first count is 257 and the sec- ond count becomes 1. this verification is unnecessary im- mediately after a reset. changing the clock source while controlling count operation will cor- rupt the binary counter value.
87 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (11) set both tm2ld and tm3ld to 0, and both tm2en and tm3en to 0. if this setting is omitted, the binary counter may not start at the first cycle. (12) set tm2ld and tm3ld to 0, and tm2en and tm3en to 1. this starts the timer. counting starts at the beginning of the next cycle. when the tm2bc value and the tm3bc value reache 0, a timer 3 underflow interrupt request occurs as soon as the tm2br value x 3f and the tm3br value x 9c are loaded. 00 f9 00 f9 f8 f7 f6 f5 f4 f9 f8 f7 00 f8 00 f9 f8 00 02 00 00 3f 00 00 9c 00 f9 f7 ff 00 3f ff 00 00 9c sysclk tm0br tm0bc tm0 output tm2br tm2bc timer 2 cascade signal tm3br tm3bc procedure (1) (3)(4) (2) (5) (7) (8) (9) (10)(11) (6) (12) 3f 9c f3 00 00 9b 9c 01 figure 4-2-5 interval timer timing
88 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-3 16-bit timer setup examples 4-3-1 event counter using 16-bit timer the event counter setup procedures for timer 6 and timer 7 are same ex- cept the up/down counting selection. in this example, timer 6 counts tm6iob pin input (sysclk/2 or less, 5 mhz or less with a 20-mhz oscillaor) and generates an interrupt on the second cycle and fifth cycle. 5 14 13 12 11 10 1 9876543210 6 m t n e 6 m t d l n 6 m t 1 d u 6 m t 0 d u 6 m t e g t 6 m t e n o 6 m t 1 d m 6 m t 0 d m 6 m t r l c e 6 m t p l 6 m t l e s a 6 m t 2 s 6 m t 1 s 6 m t 0 s 00000000010010 tm6md: x?0fe30 stop tm6bc counting and initial- ize (clear) tm6bc and rs.f.f. interrupt enable setup (1) enable interrupts. at the same time, clear all prior interrupt requests. set g6lv[2:0] bits of the g6icr to the interrupt level of 6 to 0, tm6air and tm6bir to 0, and tm6aie and tm6bie to 1. for example, write x?600 to the g6icr register. thereafter, an interrupt occurs when the timer 6 capture a and the timer 6 capture b occur. timer 6 setup (2) set the operating mode to the timer 6 mode register (tm6md). verify that count- ing is stopped and an interrupt is disabled. select up counting or down counting. select tm6iob as the timer 6 clock source. (3) set the timer 6 divisor. since timer 6 divides tm6iob pin input by 5, set 4 to the timer 6 compare/capture register a (tm6ca). (the valid range for tm6ca is 1 to x?ffe?) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 a c 6 m t 4 1 a c 6 m t 3 1 a c 6 m t 2 1 a c 6 m t 1 1 a c 6 m t 0 1 a c 6 m t 9 a c 6 m t 8 a c 6 m t 7 a c 6 m t 6 a c 6 m t 5 a c 6 m t 4 a c 6 m t 3 a c 6 m t 2 a c 6 m t 1 a c 6 m t 0 a c 0000000000000100 tm6ca: x?0fe34 (4) set the phase difference for timer 6. since the phase difference is 2 cycles, set 1 to the timer 6 compare/capture register b (tm6cb). (the valid range for tm6cb is -1 tm6cb < tm6ca.) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 b c 6 m t 4 1 b c 6 m t 3 1 b c 6 m t 2 1 b c 6 m t 1 1 b c 6 m t 0 1 b c 6 m t 9 b c 6 m t 8 b c 6 m t 7 b c 6 m t 6 b c 6 m t 5 b c 6 m t 4 b c 6 m t 3 b c 6 m t 2 b c 6 m t 1 b c 6 m t 0 b c 0000000000000001 tm6cb: x?0fe38 use the mov instruction to set the data and always use 16-bit write op- erations. in the single buffer mode, both tm6ca and tm6cb are compared to tm6bc. the tm6cb value is set to -1 by writing x ffff to tm6cb. when tm6cb is not compared to tm6bc, the tm6cb value is set to -1 .
89 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (5) set tm6nld and tm6en of the timer 6 mode register (tm6md) to 1 and 0 respectively. this enables tm6bc, t.f.f and rs.f.f. tm6md: x?0fe30 figure 4-3-1 event counter timing if this step is omitted, tm6bc may not count during the first cycle. do not change other bits in the tm6md register at the same time. 5 14 13 12 11 10 1 9876543210 6 m t n e 6 m t d l n 6 m t 1 d u 6 m t 0 d u 6 m t e g t 6 m t e n o 6 m t 1 d m 6 m t 0 d m 6 m t r l c e 6 m t p l 6 m t l e s a 6 m t 2 s 6 m t 1 s 6 m t 0 s 01 000000010010 (6) set both tm6nld and tm6en to 1. this starts the timer 6. counting starts at the beginning of the next cycle. when sysclk operates (in normal and halt modes), the external tm6iob input is sampled on sysclk. when sysclk stops (in stop mode), tm6bc counts on the tm6iob input. select the oscillation clock/4 (5 mhz with a 20-mhz oscillator) or less as the event counter clock. figure 4-3-1 shows the example of generating an interrupt dur- ing up counting. tm6ca tm6cb tm6bc tm6iob interrupts b 0000 0003 0000 0001 0004 0001 0002 0004 0003 0001 0002 0004 b a a
90 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers pin setup (1) set the tm6ioa pin to output using the port 8 i/o control register (p8dir) and the port 8 output mode register (p8md). use the mov instruction to set the data and always use 16-bit write op- erations. 76543210 8 p 7 r i d 8 p 6 r i d 8 p 5 r i d 8 p 4 r i d 8 p 3 r i d 8 p 2 r i d 8 p 1 r i d 8 p 0 r i d 01000000 p8dir: x?0ffe8 stop tm6bc counting and initial- ize (clear) tm6bc and rs.f.f. 4-3-2 pwm output using 16-bit timer the pwm output setup procedures for timer 6 and timer 7 are same except the up/down counting selection. in this example, timer 6 divides sysclk by 5 and outputs pwm signal on the fifth cycle. the duty is 2:3. therefore, set the divisor of 5 (the set value is 4 ) to the timer 6 compare/capture register a and the cycle of 2 (the set value is 1 ) to the timer 6 compare/ capture b. 76543210 8 p 7 d m 8 p 6 d m 8 p 5 d m 8 p 4 d m 8 p 3 d m 8 p 2 d m 8 p 1 d m 8 p 0 d m 01000000 p8md: x?0fff8 5 14 13 12 11 10 1 9876543210 6 m t n e 6 m t d l n 6 m t 1 d u 6 m t 0 d u 6 m t e g t 6 m t e n o 6 m t 1 d m 6 m t 0 d m 6 m t r l c e 6 m t p l 6 m t l e s a 6 m t 2 s 6 m t 1 s 6 m t 0 s 00 000001010011 tm6md: x?0fe30 timer 6 setup (2) set the operating mode to the timer 6 mode register (tm6md). verify that count- ing is stopped and an interrupt is disabled. select up counting or down counting. select sysclk as the timer 6 clock source. select the double buffer operating mode. (3) set the timer 6 divisor. since timer 6 divides sysclk by 5, set 4 to the timer 6 compare/capture register a (tm6ca). (the valid range for tm6ca is 1 to x fffe .) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 a c 6 m t 4 1 a c 6 m t 3 1 a c 6 m t 2 1 a c 6 m t 1 1 a c 6 m t 0 1 a c 6 m t 9 a c 6 m t 8 a c 6 m t 7 a c 6 m t 6 a c 6 m t 5 a c 6 m t 4 a c 6 m t 3 a c 6 m t 2 a c 6 m t 1 a c 6 m t 0 a c 0000000000000100 tm6ca: x?0fe34
91 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers tm6cax and tm6cbx are valid only when the timer 6 compare/cap- ture register is set to double buffer mode. (4) set the timer 6 duty. since the duty is 2/5 of sysclk, set 1 to the timer 6 compare/capture register b (tm6cb). (the valid range for tm6cb is -1 tm6cb < tm6ca.) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 b c 6 m t 4 1 b c 6 m t 3 1 b c 6 m t 2 1 b c 6 m t 1 1 b c 6 m t 0 1 b c 6 m t 9 b c 6 m t 8 b c 6 m t 7 b c 6 m t 6 b c 6 m t 5 b c 6 m t 4 b c 6 m t 3 b c 6 m t 2 b c 6 m t 1 b c 6 m t 0 b c 0000000000000001 tm6cb: x?0fe38 (5) in the double buffer mode, compare tm6bc to tm6cax. the tm6cax is updated when tm6cax = tm6bc, so that tm6cax remains x 0000 before tm6bc starts counting. therefore, to load the tm6ca value to tm6cax, write the dummy data to tm6cax. (the dummy data can be any values.) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 x a c 6 m t 4 1 x a c 6 m t 3 1 x a c 6 m t 2 1 x a c 6 m t 1 1 x a c 6 m t 0 1 x a c 6 m t 9 x a c 6 m t 8 x a c 6 m t 7 x a c 6 m t 6 x a c 6 m t 5 x a c 6 m t 4 x a c 6 m t 3 x a c 6 m t 2 x a c 6 m t 1 x a c 6 m t 0 x a c tm6cax: x?0fe36 (6) in the double buffer mode, compare tm6bc to tm6cbx. the tm6cbx is updated when tm6cbx = tm6bc, so that tm6cbx remains x 0000 before tm6bc starts counting. therefore, to load the tm6ca value to tm6cbx, write the dummy data to tm6cbx. (the dummy data can be any values.) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 x b c 6 m t 4 1 x b c 6 m t 3 1 x b c 6 m t 2 1 x b c 6 m t 1 1 x b c 6 m t 0 1 x b c 6 m t 9 x b c 6 m t 8 x b c 6 m t 7 x b c 6 m t 6 x b c 6 m t 5 x b c 6 m t 4 x b c 6 m t 3 x b c 6 m t 2 x b c 6 m t 1 x b c 6 m t 0 x b c tm6cbx: x?0fe3a the setup steps after step (6) are the same as steps (5) and (6) in 4-3-1 event counter using 16-bit timer . the tm6cb value is set to -1 by writing x ffff to tm6cb. when tm6cb is not compared to tm6bc, the tm6cb value is set to -1 .
92 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers tm6en tm6bc sysclk tm6ca tm6cb tm6ioa interrupts 00012 0 34012340123 b 0001 b ab a 0004 figure 4-3-2 pwm timing when timer n changes the duty of pwm output waveforms dynamically, the pwm output waveforms and interrupts may corrupt at the timing of changing the tmncb value in the single buffer mode. in the double buffer mode, the corrupt of pwm output waveforms and interrupts does not occur at any timing of changing the tmncb value. this corrupt does not occur even when the output waveforms consist of 1s and 0s. tmnen tmncb write tmnbc sysclk clrbc tmncb tmncbx s r tmnioa interrupts 01234 0 01234012340123 31 31 b a a a b b b figure 4-3-3 pwm timing in double buffer mode
93 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers pin setup (1) set the tm6ioa pin to output using the port 8 i/o control register (p8dir) and the port 8 output mode register (p8md). 76543210 8 p 7 r i d 8 p 6 r i d 8 p 5 r i d 8 p 4 r i d 8 p 3 r i d 8 p 2 r i d 8 p 1 r i d 8 p 0 r i d 11000000 p8dir: x?0ffe8 4-3-3 two-phase pwm output using 16-bit timer the two-phase pwm output setup procedures for timer 6 and timer 7 are same except the up/down counting selection. in this example, timer 6 di- vides sysclk by 5 and outputs two-phase pwm signal on the fifth cycle. the phase difference is 2 cycles. therefore, set the divisor of 5 (the set value is 4 ) to the timer 6 compare/capture register a and the cycle of 2 (the set value is 1 ) to the timer 6 compare/capture b. 76543210 8 p 7 d m 8 p 6 d m 8 p 5 d m 8 p 4 d m 8 p 3 d m 8 p 2 d m 8 p 1 d m 8 p 0 d m 11000000 p8md: x?0fff8 5 14 13 12 11 10 1 9876543210 6 m t n e 6 m t d l n 6 m t 1 d u 6 m t 0 d u 6 m t e g t 6 m t e n o 6 m t 1 d m 6 m t 0 d m 6 m t r l c e 6 m t p l 6 m t l e s a 6 m t 2 s 6 m t 1 s 6 m t 0 s 00 000001010010 tm6md: x?0fe30 timer 6 setup (2) set the operating mode to the timer 6 mode register (tm6md). verify that count- ing is stopped and an interrupt is disabled. select up counting or down counting. select tm6iob as the timer 6 clock source. (3) set the timer 6 divisor. since timer 6 divides tm6iob pin input by 5, set 4 to the timer 6 compare/capture register a (tm6ca). (the valid range for tm6ca is 1 to x fffe .) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 a c 6 m t 4 1 a c 6 m t 3 1 a c 6 m t 2 1 a c 6 m t 1 1 a c 6 m t 0 1 a c 6 m t 9 a c 6 m t 8 a c 6 m t 7 a c 6 m t 6 a c 6 m t 5 a c 6 m t 4 a c 6 m t 3 a c 6 m t 2 a c 6 m t 1 a c 6 m t 0 a c 0000000000000100 tm6ca: x?0fe34 use the mov instruction to set the data and always use 16-bit write op- erations. stop tm6bc counting and initial- ize (clear) tm6bc and rs.f.f. this verification is unnecessary im- mediately after a reset.
94 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (4) set the phase difference of timer 6. since the phase difference is two cycles of prescaler 0, set 1 to the timer 6 compare/capture register b (tm6cb). (the valid range for tm6cb is -1 < tm6cb < tm6ca.) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 b c 6 m t 4 1 b c 6 m t 3 1 b c 6 m t 2 1 b c 6 m t 1 1 b c 6 m t 0 1 b c 6 m t 9 b c 6 m t 8 b c 6 m t 7 b c 6 m t 6 b c 6 m t 5 b c 6 m t 4 b c 6 m t 3 b c 6 m t 2 b c 6 m t 1 b c 6 m t 0 b c 0000000000000001 tm6cb: x?0fe38 (5) in the double buffer mode, compare tm6bc to tm6cax. the tm6cax is updated when tm6cax = tm6bc, so that tm6cax remains x 0000 before tm6bc starts counting. therefore, to load the tm6ca value to tm6cax, write the dummy data to tm6cax. (the dummy data can be any values.) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 x a c 6 m t 4 1 x a c 6 m t 3 1 x a c 6 m t 2 1 x a c 6 m t 1 1 x a c 6 m t 0 1 x a c 6 m t 9 x a c 6 m t 8 x a c 6 m t 7 x a c 6 m t 6 x a c 6 m t 5 x a c 6 m t 4 x a c 6 m t 3 x a c 6 m t 2 x a c 6 m t 1 x a c 6 m t 0 x a c tm6cax: x?0fe36 (6) in the double buffer mode, compare tm6bc to tm6cbx. the tm6cbx is updated when tm6cbx = tm6bc, so that tm6cbx remains x 0000 before tm6bc starts counting. therefore, to load the tm6ca value to tm6cbx, write the dummy data to tm6cbx. (the dummy data can be any values.) 5 14 13 12 11 10 1 9876543210 6 m t 5 1 x b c 6 m t 4 1 x b c 6 m t 3 1 x b c 6 m t 2 1 x b c 6 m t 1 1 x b c 6 m t 0 1 x b c 6 m t 9 x b c 6 m t 8 x b c 6 m t 7 x b c 6 m t 6 x b c 6 m t 5 x b c 6 m t 4 x b c 6 m t 3 x b c 6 m t 2 x b c 6 m t 1 x b c 6 m t 0 x b c tm6cbx: x?0fe3a the setup steps after step (6) are the same as steps (5) and (6) in 4-3-1 event counter using 16-bit timer . tm6en tm6bc sysclk tm6ca tm6cb tm6ioa interrupts 00012 0 34012340123 b 0001 b ab a 0004 tm6iob figure 4-3-4 two-phase pwm timing tm6cax and tm6cbx are valid only when the timer 6 compare/cap- ture register is set to double buffer mode.
95 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers when timer n changes the duty of pwm output waveforms dynamically, the pwm output waveforms and interrupts may corrupt at the timing of changing the tmncb value in the single buffer mode. in the double buffer mode, the corrupt of pwm output waveforms and interrupts does not occur at any timing of changing the tmncb value. this corrupt does not occur even when the output waveforms consist of 1s and 0s. tmnen tmncb write tmnbc clock output clrbc tmncb tmncbx s r tmnioa interrupts 01234 0 01234012340123 31 31 b a a a b b b tmniob figure 4-3-5 two-phase pwm timing in double buffer mode
96 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-3-4 one-phase capture input using 16-bit timer the one-phase capture input setup procedures for timer 6 and timer 7 are same except the up/down counting selection. in this example, timer 7 di- vides sysclk by 65536 and measures how long the tm7ioa input is high. an interrupt occurs on the capture b and the width where the tm7ioa input is high is calculated by the instruction (tmncb - tmnca). 5 14 13 12 11 10 1 9876543210 7 m t n e n 7 m t d l 7 m t 1 d u 7 m t 0 d u 7 m t e g t 7 m t e n o 7 m t 1 d m 7 m t 0 d m 7 m t r l c e 7 m t p l 7 m t l e s a 7 m t 2 s 7 m t 1 s 7 m t 0 s 00 000010000011 tm7md: x?0fe40 interrupt enable setup (1) enable interrupts. at the same time, clear all prior interrupt requests. set g7lv[2:0] bits of the g7icr to the interrupt level of 6 to 0, tm7bir 7 and tm7bie to 0 and 1 respectively. for example, write x 4400 to the g7icr register. thereafter, an interrupt occurs when the timer 7 capture b occurs. timer 7 setup (2) set the operating mode to the timer 7 mode register (tm7md). verify that count- ing is stopped and an interrupt is disabled. select up counting or down counting. set tm7lp to 0 to count the loop of 0 to x ffff . select sysclk as the timer 7 clock source. (3) set tm7nld and tm7en of the tm7md register to 1 and 0 respectively. this enables tm7bc, t.f.f and rs.f.f. (4) set both tm7nld and tm7en to 1. this starts the timer 7. counting starts at the beginning of the next cycle. stop tm7bc counting and initial- ize (clear) tm7bc and rs.f.f. use the mov instruction to set the data and always use 16-bit write op- erations. if this step is omitted, tm7bc may not count during the first cycle.
97 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers compare/capture register setup (5) when tm7md[1:0] = 10 (the capture is selected), tm7ca and tm7cb are reserved for read operations. when setting tm7ca and tm7cb is required, first set tm7md[1:0] to 00 . 5 14 13 12 11 10 1 9876543210 7 m t 5 1 a c 7 m t 4 1 a c 7 m t 3 1 a c 7 m t 2 1 a c 7 m t 1 1 a c 7 m t 0 1 a c 7 m t 9 a c 7 m t 8 a c 7 m t 7 a c 7 m t 6 a c 7 m t 5 a c 7 m t 4 a c 7 m t 3 a c 7 m t 2 a c 7 m t 1 a c 7 m t 0 a c tm7ca: x?0fe44 5 14 13 12 11 10 1 9876543210 7 m t 5 1 b c 7 m t 4 1 b c 7 m t 3 1 b c 7 m t 2 1 b c 7 m t 1 1 b c 7 m t 0 1 b c 7 m t 9 b c 7 m t 8 b c 7 m t 7 b c 7 m t 6 b c 7 m t 5 b c 7 m t 4 b c 7 m t 3 b c 7 m t 2 b c 7 m t 1 b c 7 m t 0 b c tm7cb: x?0fe48 tm7ca is captured on the rising edge of tm7ioa and tm7cb is cap- tured on the falling edge of tm7ioa. interrupt processing and width calculation (6) execute interrupt processing. the interrupt processing specifies the interrupt group and vector, and clears irfn. (7) calculate the width. store the tm7ca value and tm7cb value to the data regis- ter and subtract tm7ca from tm7cb. ignore c and v flags. the width is calcu- lated correctly even though the tm7ca value is greater than the tm7cb value by setting tm7lp to 0. the following figure shows 000a - 0007 = 0003 or 3 cycles. tm7en tm7bc sysclk tm7ca tm7cb tm7ioa interrupts 01234 0 56 789 abcdef101112 07 0a a-7=3 3 cycles b figure 4-3-6 one-phase capture timing load the tm7ca value and tm7cb value during interrupt processing. the width is calculated by ignoring flags even though the tm7ca value is greater than the tm7cb value.
98 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-3-5 two-phase capture input using 16-bit timer the two-phase capture input setup procedures for timer 6 and timer 7 are same except the up/down counting selection. in this example, timer 7 di- vides sysclk by 65536 and measures the width from positive edge of the tm7ioa input to the positive edge of tm7iob input. an interrupt occurs on the capture b and the width is calculated by the instruction (tmncb - tmnca). 5 14 13 12 11 10 1 9876543210 7 m t n e n 7 m t d l 7 m t 1 d u 7 m t 0 d u 7 m t e g t 7 m t e n o 7 m t 1 d m 7 m t 0 d m 7 m t r l c e 7 m t p l 7 m t l e s a 7 m t 2 s 7 m t 1 s 7 m t 0 s 00 000011000011 tm7md: x?0fe40 interrupt enable setup (1) enable interrupts. at the same time, clear all prior interrupt requests. set g7lv[2:0] bits of the g7icr to the interrupt level of 6 to 0, tm7bir and tm7bie to 0 and 1 respectively. for example, write x 4400 to the g7icr register. thereafter, an interrupt occurs when the timer 7 capture b occurs. timer 7 setup (2) set the operating mode to the timer 7 mode register (tm7md). verify that count- ing is stopped and an interrupt is disabled. select up counting or down counting. set tm7lp to 0 to count the loop of 0 to x ffff . select sysclk as the timer 7 clock source. stop tm7bc counting and initial- ize (clear) tm7bc and rs.f.f. use the mov instruction to set the data and always use 16-bit write op- erations. tm7ca is captured on the rising edge of tm7ioa and tm7cb is cap- tured on the rising edge of tm7iob. the setup steps after step (2) are the same as steps (3) to (7) in 4-3-4 one-phase capture input using 16-bit timer . the figure 4-3-7 shows 000a - 0007 = 0003 or 3 cycles.
99 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers tm7en tm7bc sysclk tm7ca tm7cb tm7ioa tm7iob interrrupts b 01234 0 56789abcdef101112 07 0a a-7=3 3 c y cles figure 4-3-7 two-phase capture timing
100 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-3-6 t wo-phase encoder input using 16-bit timer (4x) the two-phase encoder input setup procedures for timer 6 and timer 7 are same. in this example, timer 7 inputs the two-phase encoder (4x) and counts up/down. an interrupt occurs when the tm7bc reaches the set value. 5 14 13 12 11 10 1 9876543210 7 m t n e n 7 m t d l 7 m t 1 d u 7 m t 0 d u 7 m t e g t 7 m t e n o 7 m t 1 d m 7 m t 0 d m 7 m t r l c e 7 m t p l 7 m t l e s a 7 m t 2 s 7 m t 1 s 7 m t 0 s 00 000000010100 tm7md: x?0fe40 interrupt enable setup (1) enable interrupts. at the same time, clear all prior interrupt requests. set g7lv[2:0] bits of the g7icr to the interrupt level of 6 to 0, tm7bir and tm7bie to 0 and 1 respectively. for example, write x 4400 to the g7icr register. thereafter, an interrupt occurs when the timer 7 capture b occurs. timer 7 setup (2) set the operating mode to the timer 7 mode register (tm7md). verify that count- ing is stopped and an interrupt is disabled. select up counting or down counting. set tm7lp to 1 when tm7bc starts loop counting from the tm7ca value. set tm7lp to 0 when tm7bc counts the loop of 0 to x ffff . select two-phase encoder (4x) as the timer 7 clock source. stop tm7bc counting and initial- ize (clear) tm7bc and rs.f.f. use the mov instruction to set the data and always use 16-bit write op- erations. (3) set the timer 7 looping value (the valid range is 1 to x ffff ). when writing x 1fff to tm7ca, the tm7bc counts from 0 to x 1fff . 5 14 13 12 11 10 1 9876543210 7 m t 5 1 a c 7 m t 4 1 a c 7 m t 3 1 a c 7 m t 2 1 a c 7 m t 1 1 a c 7 m t 0 1 a c 7 m t 9 a c 7 m t 8 a c 7 m t 7 a c 7 m t 6 a c 7 m t 5 a c 7 m t 4 a c 7 m t 3 a c 7 m t 2 a c 7 m t 1 a c 7 m t 0 a c 0001111111111111 tm7ca: x?0fe44 whenever the up or down counter reaches the tm7ca value, a compare/capture a inter- rupt occurs at the beginning of the next cycle.
101 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (4) set the value for a timer 7 interrupt when the interrupt occurs at the tm7cb value. (the valid range is 0 to tm7ca.) when the up or down counter reaches this value, a compare/capture b interrupt occurs at the beginning of the next cycle. set the value for timer 7 interrupt when the tm7bc counts from 0 to x ffff . (the valid range is 0 to x ffff .) (5) set tm7nld and tm7en to 1 and 0 respectively. this enables tm7bc, t.f.f and rs.f.f. do not change other bits of the tm7md register. (6) set both tm7nld and tm7en to 1. this starts timer 7. counting starts at the beginning of the next cycle. interrupt processing (6) execute interrupt processing. the interrupt processing specifies the interrupt group and vector, and clears irfn. the following figure shows the count direction. tm7ioa tm7iob 0 1 up counting down counting 1 00 0 1 1 tm7ca tm7cb tm7bc tm7ioa tm7iob interrupts b 1fff 1ffe 0000 1ffd 1ffe 1fff 0000 0001 0fff 1fff 1000 1000 1001 figure 4-3-8 two-phase encoder input timing if this step is omitted, tm7bc may not count during the first cycle.
102 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-3-7 one-shot pulse output using 16-bit timer the one-shot pulse setup procedures for timer 6 and timer 7 are same. in this example, timer 7 generates a one-shot pulse. the pulse width is 2 cycles of sysclk. 5 14 13 12 11 10 1 9876543210 7 m t n e n 7 m t d l 7 m t 1 d u 7 m t 0 d u 7 m t e g t 7 m t e n o 7 m t 1 d m 7 m t 0 d m 7 m t r l c e 7 m t p l 7 m t l e s a 7 m t 2 s 7 m t 1 s 7 m t 0 s 00 000100010011 tm7md: x?0fe40 timer 7 setup (1) set the operating mode to the timer 7 mode register (tm7md). verify that count- ing is stopped and an interrupt is disabled. select up counting. select sysclk as the timer 7 clock source. (2) set the timer 7 pulse width to tm7ca. (the valid range is 1 to x ffff .) since the timer 7 pulse width is 2 cycles of sysclk, write 3 to tm7ca. tm7bc counts from 0 to 3, and tm7ioa outputs high while tm7bc counts from 2 to 3. 5 14 13 12 11 10 1 9876543210 7 m t 5 1 a c 7 m t 4 1 a c 7 m t 3 1 a c 7 m t 2 1 a c 7 m t 1 1 a c 7 m t 0 1 a c 7 m t 9 a c 7 m t 8 a c 7 m t 7 a c 7 m t 6 a c 7 m t 5 a c 7 m t 4 a c 7 m t 3 a c 7 m t 2 a c 7 m t 1 a c 7 m t 0 a c 0000000000000011 tm7ca: x?0fe44 (3) write 1 to tm7cb. 5 14 13 12 11 10 1 9876543210 7 m t 5 1 b c 7 m t 4 1 b c 7 m t 3 1 b c 7 m t 2 1 b c 7 m t 1 1 b c 7 m t 0 1 b c 7 m t 9 b c 7 m t 8 b c 7 m t 7 b c 7 m t 6 b c 7 m t 5 b c 7 m t 4 b c 7 m t 3 b c 7 m t 2 b c 7 m t 1 b c 7 m t 0 b c 0000000000000001 tm7cb: x?0fe48 (4) set tm7nld and tm7en to 1 and 0 respectively. this enables tm7bc, t.f.f and rs.f.f. (5) set tm7en to 1 when tm7iob rises. counting starts at the beginning of the next cycle after tm7iob rises. stop tm7bc counting and initial- ize (clear) tm7bc and rs.f.f. use the mov instruction to set the data and always use 16-bit write op- erations. if this step is omitted, tm7bc may not count during the first cycle. do not output athe first one-shot pulse when tm7cb is set to 0 . tm7en is substitute for the busy flag for one-shot pulse.
103 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers figure 4-3-9 shows the one-shot pulse output timing. set tm7en on the falling edge of tm7iob and start counting from the next cycle. before counting starts, tm7bc is 0, the initial value of tm7ioa is 0, and a reset (r) signal and a set (s) signal cannot be output. when counting starts, tm7bc changes from 0 to 1 and the s signal is output. tm7ioa becomes 1 and the pulse is output. tm7bc reaches 3, tm7bc resets and changes from 3 to 0. at the same time, the r signal is output and tm7ioa outputs 0. because tm7one is set to 1, the tm7en flag is also reset and counting stops. when tm7iob rises again, tm7en is set and the same operation is repeated. as a result, the one-shot pulse is output. tm7ca tm7cb tm7en tm7iob input s r tm7ioa output 0000 0003 0000 0001 0003 0001 0002 0003 0001 0002 0000 tm7bc sysclk figure 4-3-9 one-shot pulse output timing
104 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers 4-3-8 external count direction control using 16-bit timer the external count direction control setup procedures for timer 6 and timer 7 are same. in this example, timer 7 counts sysclk and controls the counting direction using tm7ioa. an interrupt occurs when tm7bc reaches the set value. interrupt enable setup (1) enable interrupts. at the same time, clear all prior interrupt requests. set g7lv[2:0] bits of the g7icr to the interrupt level of 6 to 0, tm7bir and tm7bie to 0 and 1 respectively. for example, write x 4400 to the g7icr register. thereafter, an interrupt occurs when the timer 7 capture b occurs. timer 7 setup (2) set the operating mode to the timer 7 mode register (tm7md). verify that count- ing is stopped and an interrupt is disabled. the count direction is up when tm7ioa pin is 1 while the count direction is down when tm7ioa is 0. select sysclk as the timer 7 clock source. (3) set the timer 7 looping value (the valid range is 1 to x ffff ). when writing x 1fff to tm7ca, the tm7bc counts from 0 to x 1fff . the up or down counter reaches the tm7ca value, a compare/capture a interrupt occurs at the beginning of the next cycle. stop tm7bc counting and initial- ize (clear) tm7bc and rs.f.f. use the mov instruction to set the data and always use 16-bit write op- erations. 5 14 13 12 11 10 1 9876543210 7 m t n e n 7 m t d l 7 m t 1 d u 7 m t 0 d u 7 m t e g t 7 m t e n o 7 m t 1 d m 7 m t 0 d m 7 m t r l c e 7 m t p l 7 m t l e s a 7 m t 2 s 7 m t 1 s 7 m t 0 s 00 100000010011 tm7md: x?0fe40 (4) set the value for a timer 7 interrupt when the interrupt occurs at the tm7cb value. (the valid range is 0 to tm7ca.) when the up or down counter reaches this value, a compare/capture b interrupt occurs at the beginning of the next cycle. set the value for timer 7 interrupt when the tm7bc counts from 0 to x ffff . (the valid range is 0 to x ffff .) 5 14 13 12 11 10 1 9876543210 7 m t 5 1 a c 7 m t 4 1 a c 7 m t 3 1 a c 7 m t 2 1 a c 7 m t 1 1 a c 7 m t 0 1 a c 7 m t 9 a c 7 m t 8 a c 7 m t 7 a c 7 m t 6 a c 7 m t 5 a c 7 m t 4 a c 7 m t 3 a c 7 m t 2 a c 7 m t 1 a c 7 m t 0 a c 0001111111111111 tm7ca: x?0fe44
105 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers (5) set tm7nld and tm7en to 1 and 0 respectively. this enables tm7bc, t.f.f and rs.f.f. do not change other bits of the tm7md register. (6) set both tm7nld and tm7en to 1. this starts timer 7. counting starts at the beginning of the next cycle. interrupt processing (6) execute interrupt processing. the interrupt processing specifies the interrupt group and vector, and clears irfn. the following figure shows the count direction. timer 7 controls the count direction using tm7ioa or tm7iob. the count direction becomes the opposite edge of the count edge (shown as ? in figure 4-3-10). figure 4-3- 10 shows the external count direction control timing and the example of becoming down counting from up counting and generating an interrupt. b tm7ca tm7cb tm7bc sysclk tm7ioa interrupts count direction 0000 1fff 1000 0003 0001 0002 1000 1fff 1ffe 1ffd 0000 1ffe 1fff 1001 down down up up up up up up up up up figure 4-3-10 external count direction control timing if this step is omitted, tm7bc may not count during the first cycle.
106 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers timer 7 setup (1) set the operating mode to the timer 7 mode register (tm7md). verify that count- ing is stopped and an interrupt is disabled. select up counting. set tm7eclr to 1 becuase tm7bc is reset by tm7ic pin asynchronously. select sysclk as the timer 7 clock source. 5 14 13 12 11 10 1 9876543210 7 m t n e n 7 m t d l 7 m t 1 d u 7 m t 0 d u 7 m t e g t 7 m t e n o 7 m t 1 d m 7 m t 0 d m 7 m t r l c e 7 m t p l 7 m t l e s a 7 m t 2 s 7 m t 1 s 7 m t 0 s 00 000000110011 tm7md: x?0fe40 5 14 13 12 11 10 1 9876543210 7 m t 5 1 a c 7 m t 4 1 a c 7 m t 3 1 a c 7 m t 2 1 a c 7 m t 1 1 a c 7 m t 0 1 a c 7 m t 9 a c 7 m t 8 a c 7 m t 7 a c 7 m t 6 a c 7 m t 5 a c 7 m t 4 a c 7 m t 3 a c 7 m t 2 a c 7 m t 1 a c 7 m t 0 a c 0001111111111111 tm7ca: x?0fe44 4-3-9 external reset control using 16-bit timer the external reset control setup procedures for timer 6 and timer 7 are same. in this example, timer 7 is reset by an external signal while counting up. (2) set the timer 7 looping value (the valid range is 1 to x ffff ). when writing x 1fff to tm7ca, the tm7bc counts from 0 to x 1fff . (3) set tm7nld and tm7en to 1 and 0 respectively. this enables tm7bc, t.f.f and rs.f.f. do not change other bits of the tm7md register. (4) set both tm7nld and tm7en to 1. this starts timer 7. counting starts at the beginning of the next cycle. stop tm7bc counting and initial- ize (clear) tm7bc and rs.f.f. use the mov instruction to set the data and always use 16-bit write op- erations. if this step is omitted, tm7bc may not count during the first cycle.
107 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers thereafter, timer 7 is reset asynchronously when tm7ic is high. this allows external synchronization easily. it can be used to adjust the motor or to initialize the timer by hardware. tm7bc sysclk tm7ic 0003 0000 0001 0002 0003 0001 0002 0000 0004 figure 4-3-11 external reset control timing
108 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 4 timers
0 1 2 3 4 5 6 7 8 9 chapter 5 serial interface
110 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface 5-1 serial interface 5-1-1 overview this lsi series contains two serial interfaces. each serial interface trans- mits and receives the data in the synchronous mode, asynchronous mode and i 2 c mode. the maximum baud speed in synchronous mode is sysclk/ 4. the maximum baud speed in asynchronous mode is 312,500 bps with a 20-mhz oscillator. (the baud speed can be set to 312,500 bps or more by changing the oscillation frequency.) sbo0 sbt0 sbi0 sbo1 sbt1 sbi1 timer 2 underflow timer 3 underflow txc txd rxc rxd transmitter receiver txc txd rxc rxd transmitter receiver transmission end interrupt 0 reception end interrupt 0 transmission end interrupt 0 reception end interrupt 0 figure 5-1-1 serial interface configuration synchronous serial interface asynchronous serial interface i 2 c parity character length 8-bit bit order lsb first, msb first lsb msb clock source timer 2/16 or timer 3/16 timer 2/16 or timer 3/16 timer 2/16 or timer 3/16 external clock timer 2/2 (ch0) timer 3/2 (ch1) max. transfer speed 2,500,000 bps 312,500 bps 100,000 bps (with a 20-mhz oscillator) (with a 20-mhz oscillator) error detect parity error parity error slave response overrun error overrun error framing error buffer interrupt none, 0, 1, even, odd 7-bit, 8-bit independent transmit/receive buffer (s in g l e tr a n s mi t b u ff e r , d oub l e r ece i ve transmission end interru p t, rece p tion end interru p t table 5-1-1 serial interface features
111 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface serial interface 0 serial interface 1 serial control register serial 0 control register (sc0ctr), x'00fd80' serial 1 control register (sc1ctr), x'00fd90' serial transmit/receive register serial 0 transmit/receive register (sc0trb), x'00fd82' serial 1 transmit/receive register (sc1trb), x'00fd92' serial status register serial 0 status register (sc0str), x'00fd83' serial 1 status register (sc1str), x'00fd93' 5-1-2 control registers three registers control the serial interface: serial control register (scnctr), serial transmit/receive register (scntrb) and serial status register (scnstr). table 5-1-2 list of serial interface control registers the serial control register (scnctr) sets the operating conditions for serial interface. this register controls clock source selection, parity bit selection, protocol selection and transmit/receive enable. the transmit data is written to the serial transmit/receive register (scntrb), while the receive data is written to the scntrb register. the transmission starts at the end of the first cycle or second cycle of the transfer clock (timer 2 underflow or timer 3 udnerflow) after the data is written to scntrb. the serial transmission is operated in double buffer mode. after the reception is completed, the data is set to the scntrb register. the receive data is loaded when an interrupt occurs or the scnrxa flag of the scnstr register is 1. the serial status register (scnstr) reads the status of error detection of serial interface. an overrun error occurs when the next data is received before the received data is loaded by scntrb. an error does not occur on the next cycle by reading the scntrb register. the overrun error data is updated when the last bit (the 7th bit or the 8th bit) of the data is received. a parity error occurs when the parity bit is 1 although it is supposed to 0, when the parity bit is 0 although it is supposed to 1, when the parity bit is odd although it is even and when the parity bit is even although it is supposed to set odd. the parity error data is updated when the parity bit is received. a framing error occurs when the stop bit is 0. the framing error data is updated when the stop bit is received. figure 5-1-2 shows the timing when each bit of the serial status register (scnstr). igonore msb (bit 7) in the 7-bit transmission. write the data to the serial transmit/ receive register after verifying the data is not in transmission by check- ing the scntbsy of the scnstr register or a transmission end inter- rupt. the serial transmission may not occur if writing to the serial transmit/receive register during the transmission is operated. the msb (bit 7) becomes 0 in the 7-bit reception.
112 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface figure 5-1-2 scnstr change timing asynchronous/synchronous timing sbo write data to scntrb reset even when transmission is disabled. scntbsy transmission interrupt b0 b2 b3 b4 b5 b6 pty st b1 transmission sbi scnrbsy reset even when reception is disabled. reset even when reception is disabled. reception interrupt rxa read data of scntrb scnoe (overrun error) scnpe (parity error) scnfe (framing error) b0 b2 b3 b4 b5 b6 pty st b1 update update update reception i 2 c timing sbo sbt scnsts start detect scntrb write scnsps after reset, the signal is low during the first i c transmission. the signal is high during other transmission. 2
113 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface 5-1-3 serial interface connection there are six serial interface connecting methods. asynchronous mode the serial interface can connect using either simplex transfer or duplex transfer mode. sbo sbi sbo sbi transmit receive sbo sbi sbo sbi transmit/receive transmit/receive figure 5-1-3 asynchronous connection simplex connection duplex connection synchronous mode the serial interface can connect using either simplex transfer, duplex transfer or half- duplex transfer mode. sbo sbi sbo sbi transmit receive sbt sbt sbo sbi sbo sbi sbt sbt transmit/receive transmit/receive figure 5-1-4 synchronous connection simplex connection duplex connection sbo sbi sbo sbi sbt sbt transmit/receive transmit/receive half-duplex connection when the data cannot be transmitted in half-duplex mode, both sbt pins become input so that they need pull-up resistors. the sbt pins connect a pull-up resistor externally or a built-in pull-up resistor by the pplu register. see chapter 7 for sbt port setup.
114 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface i 2 c mode the serial interface can connect to the devices which can slave transmit and receive. the sbo pin and sbt pin connect pull-up resistors (externally or internally). sbo sbt master transmition/reception slave transmit/receive this lsi series slave transmit/receive figure 5-1-5 i 2 c mode connection the acknowledge (ack) bit is substituted for a parity bit. in the system requiring the ack, fix the parity bit to 1 (scnpty[2:0] = 101) when this lsi master transmits the data. in that case, a parity error occurs when the ack (low level) returns from the slave. there- fore, the parity bit of the scnstr register becomes 1 when the transmission is completed normally. on the other hand, when this lsi master receives the data, fix the parity bit to 0 (scnpty[2:0] = 100) if the ack returns from the slave and set the parity bit to 1 (scnpty[2:0] = 101) if the ack does not return. during i 2 c transmission/reception, the transmit state flag of the scnstr register shows the transmission/reception in progress. asynchronous serial transfer speed in asynchronous mode, set the serial transfer clock to 16 times of transfer baud rate. the following is the baud rate calculation. baud rate (bps) = osci, osco x 1/32 x 1/timer divisor the transmission is possible if the baud rate error is within 2 %. table 5-1-3 to table 5-1- 10 show the baud rates with frequently used oscillators. the i 2 c mode is used only as the master transmission/reception in the single master system. because i 2 c mode do not control the protocol, setting the transfer baud rate and controlling the transfer start are re- quired to function the slave trans- mission/reception.
115 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface table 5-1-3 baud rate setup example in asynchronous mode external oscillator at 20 mhz baud rate divisor real time error 1200 520 1201.92 0.16 2400 260 2403.85 0.16 4800 130 4807.69 0.16 9600 65 9615.38 0.16 19200 33 18939.39 -1.36 28800 22 28409.09 -1.36 31250 20 31250.00 0.00 38400 16 39062.50 1.73 48000 13 48076.92 0.16 57600 11 56818.18 -1.36 76800 8 78125.00 1.73 153600 4 156250.00 1.73 307200 2 312500.00 1.73 312500 2 312500.00 0.00 (max) external oscillator at 19.6608 mhz baud rate divisor r eal time error 1200 520 11 81.54 -1.54 2400 260 23 63.08 -1.54 4800 130 47 26.15 -1.54 9600 65 94 52.31 -1.54 19200 32 19200.00 0.00 28800 21 29257.14 1.59 31250 20 30720.00 -1.70 38400 16 38400.00 0.00 48000 13 47261.54 -1.54 57600 11 55854.55 -3.03 76800 8 76800.00 0.00 153600 4 153600.00 0.00 307200 2 307200.00 0.00 (max) external oscillator at 17.2032 mhz baud rate divisor real time error 1200 448 1200.00 0.00 2400 224 2400.00 0.00 4800 112 4800.00 0.00 9600 56 9600.00 0.00 19200 28 19200.00 0.00 28800 19 28294.74 -1.75 31250 17 31623.53 1.20 38400 14 38400.00 0.00 48000 11 48872.73 1.82 57600 9 59733.33 3.70 76800 7 76800.00 0.00 153600 3 179200.00 16.67 268800 2 268800.00 0.00 (max) external oscillator at 16 mhz baud rate divisor r eal time error 1200 417 119 9.04 -0.08 2400 208 240 3.85 0.16 4800 104 480 7.69 0.16 9600 52 961 5.38 0.16 19200 26 19230.77 0.16 28800 17 29411.76 2.12 31250 16 31250.00 0.00 38400 13 38461.54 0.16 48000 10 50000.00 4.17 57600 9 55555.56 -3.55 76800 7 71428.57 -6.99 153600 3 16 6666.67 8.51 250000 2 25 0000.00 0.00 (max) external oscillator at 14 mhz baud rate divisor real time error 1200 368 1188.86 -0.93 2400 184 2377.72 -0.93 4800 92 4755.43 -0.93 9600 46 9510.87 -0.93 19200 23 19021.74 -0.93 28800 15 29166.67 1.27 31250 14 31250.00 0.00 38400 11 39772.73 3.57 48000 9 48611.11 1.27 57600 8 54687.50 -5.06 76800 6 72916.67 -5.06 153600 3 145833.33 -5.06 218750 2 218750.00 0.00 (max) external oscillator at 12 mhz baud rate divisor r eal time error 1200 312 12 01.92 0.16 2400 156 24 03.85 0.16 4800 78 48 07.69 0.16 9600 39 96 15.38 0.16 19200 20 18750.00 -2.34 28800 13 28846.15 0.16 31250 12 31250.00 0.00 38400 10 37500.00 -2.34 48000 8 46875.00 -2.34 57600 7 53571.43 -6.99 76800 5 75000.00 -2.34 153600 3 125000.00 -18.62 187500 2 187500.00 0.00 (max) external oscillator at 10 mhz baud rate divisor real time error 1200 260 1201.92 0.16 2400 130 2403.85 0.16 4800 65 4807.69 0.16 9600 33 9469.70 -1.36 19200 16 19531.25 1.73 28800 11 28409.09 -1.36 31250 10 31250.00 0.00 38400 8 39062.50 1.73 48000 7 44642.86 -6.99 57600 5 62500.00 8.51 76800 4 78125.00 1.73 153600 2 156250.00 1.73 156250 2 156250.00 0.00 (max) external oscillator at 8 mhz baud rate divisor r eal time error 1200 208 120 1.92 0.16 2400 104 240 3.85 0.16 4800 52 480 7.69 0.16 9600 26 961 5.38 0.16 19200 13 19230.77 0.16 28800 9 27777.78 -3.55 31250 8 31250.00 0.00 38400 7 35714.29 -6.99 48000 5 50000.00 4.17 57600 4 62500.00 8.51 76800 3 83333.33 8.51 125000 2 12 5000.00 0.00 (max) * : available with timer 0 in case of the divisor of 256 or greater. * * table 5-1-4 baud rate setup example in asynchronous mode * : available with timer 0 in case of the divisor of 256 or greater. * * table 5-1-5 baud rate setup example in asynchronous mode * : available with timer 0 in case of the divisor of 256 or greater. * table 5-1-6 baud rate setup example in asynchronous mode * : available with timer 0 in case of the divisor of 256 or greater. * table 5-1-7 baud rate setup example in asynchronous mode * : available with timer 0 in case of the divisor of 256 or greater. * table 5-1-9 baud rate setup example in asynchronous mode * : available with timer 0 in case of the divisor of 256 or greater. * table 5-1-8 baud rate setup example in asynchronous mode * : available with timer 0 in case of the divisor of 256 or greater. * table 5-1-10 baud rate setup example in asynchronous mode
116 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface setting timer is required during se- rial reception in asynchronous mode. 5-2 serial interface setup examples 5-2-1 serial transmission in asynchronous mode using timer 2 this section describes the example of serial interface 0 transmission in asyn- chronous mode with the following settings: 20 mhz oscillation baud rate = 9600 bps (sysclk/65 by timer 2) bit order: lsb 8-bit data transfer two stop bits odd parity the next data is transmitted when a transmission end interrupt occurs. serial i/f transfer clock sysclk (10 mhz) 8-bit timer timer 2 (divided by 65) serial interface divider (divided by 16) figure 5-2-1 aynchronous transmission configuration the transmission starts when the data is written to the sc0trb register. the transmis- sion starts synchronizing with timer 2 underflow. an interrupt occurs after the transmis- sion is completed and the new data is written to the sc0trb register during the interrupt service routine. the sc0tbsy flag of the sc0str register polls if an interrupt does not occur. the serial interface generates the serial transfer baud rate with timer 2 or timer 3 divided by 16. with a 20-mhz oscillator (sysclk is 10 mhz) and 9600 bps, 10 mhz/16/9600 = 65.10 therefore, set the timer 2 or timer 3 underflow to 65. pin setup set p72 pin to data output of serial interface 0. [see chapter 8 ports]
117 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface timer 2 setup (1) verify that counting is stopped with the timer 2 mode register (tm2md). 76543210 2 m t n e 2 m t d l 2 m t s1 2 m t s0 00 11 tm2md: x?0fe22 (2) set the timer 2 divisor. since the timer 2 divisor is sysclk/65, set the timer 2 base register (tm2br) to 64. (the valid range is 1 to 255.) 76543210 2 m t 7 r b 2 m t 6 r b 2 m t 5 r b 2 m t 4 r b 2 m t 3 r b 2 m t 2 r b 2 m t 1 r b 2 m t 0 r b 01000000 tm2br: x?0fe12 (3) load the tm2br value to tm2bc. to do this, set tm2ld and tm2en to 1 and 0 respectively. at the same time, select the clock source. (4) set both tm2ld and tm2en to 0. (5) set tm2ld and tm2en to 0 and 1 respectively. this starts timer 2. serial interface 0 setup (6) enable interrupts. at this point, clear all prior interrupt requests. set the g3icr register to the interrupt level (level 6 to 0), sc0tir and sc0tie to 0 and 1 respec- tively. for example, write the g3icr register to x 4400 . thereafter, a serial transmission end interrupt occurs when the data written to the serial transmit/re- ceive register is transferred. 5 14 13 12 11 10 1 9876543210 3 g 2 v l 3 g 1 v l 3 g 0 v l r 0 c s e i t 0 c s e i 2 m t e i 2 q r i e i r 0 c s r i t 0 c s r i 2 m t r i 2 q r i r i r 0 c s d i t 0 c s d i 2 m t d i 2 q r i d i 0 100010000000000 g3icr: x?0fc46 this verification is unnecessary im- mediately after a reset. do not change the clock source once you have selected it. changing the clock source while controlling count operation will corrupt the binary counter value. if this step is omitted, tm2bc may not count during the first cycle.
118 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface (7) set the operating control conditions to the serial 0 control register (sc0ctr). set asynchronous mode, lsb for bit order, timer 2/16, 8-bit data transfer, 2 stop bits and odd parity. 5 14 13 12 11 10 1 9876543210 0 c s n e t 0 c s n e r 0 c s e r b 0 c s s c 2 i 0 c s l t p 0 c s d o 0 c s m c 2 i 0 c s n l 0 c s 2 y t p 0 c s 1 y t p 0 c s 0 y t p 0 c s b s 0 c s d o p 0 c s 1 s 0 c s 0 s 1 1000 0011111001 sc0ctr: x?0fd80 (8) set the first data to be transferred to the serial 0 transmit/receive register (sc0trb). when the data to be transferred is set to the sc0trb register, the transmission starts synchronizing with timer 2. execute the interrupt service routine and trans- fer the next data when an interrupt occurs. timer 2 underflow/16 sc0trb write sbo0 interrupt request interrupt service routine sc0tbsy st b0 b1 b2 b3 b4 b5 b6 b7 pt sp sp st b0 b1 b2 b3 b4 figure 5-2-2 bit transmission timing in asynchronous mode
119 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface
120 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface 5-2-2 serial reception in synchronous mode using timer 2 this section describes the example of serial interface 0 reception in syn- chronous mode with the following settings: bit order: msb 8-bit data transfer even parity the next data is read when a reception end interrupt occurs. pin setup set p70 pin and p71 pin to serial clock input and data input of serial interface 0 respec- tively. [see chapter 8 ports] serial interface 0 setup (1) set the operating control conditions to the serial 0 control register (sc0ctr). set synchronous mode, msb for bit order, the external clock source, 8-bit data trans- fer and even parity. 5 14 13 12 11 10 1 9876543210 0 c s n e t 0 c s n e r 0 c s e r b 0 c s s c 2 i 0 c s l t p 0 c s d o 0 c s m c 2 i 0 c s n l 0 c s 2 y t p 0 c s 1 y t p 0 c s 0 y t p 0 c s b s 0 c s d o p 0 c s 1 s 0 c s 0 s 1 1001 1011100000 sc0ctr: x?0fd80 (2) enable interrupts. at this point, clear all prior interrupt requests. set the g3icr register to the interrupt level (level 6 to 0), sc0rir and sc0rie to 0 and 1 respec- tively. for example, write the g3icr register to x 4800 . thereafter, a serial reception end interrupt occurs when the data is transferred to the serial transmit/ receive register. 5 14 13 12 11 10 1 9876543210 3 g 2 v l 3 g 1 v l 3 g 0 v l r 0 c s e i t 0 c s e i 2 m t e i 2 q r i e i r 0 c s r i t 0 c s r i 2 m t r i 2 q r i r i r 0 c s d i t 0 c s d i 2 m t d i 2 q r i d i 0 100100000000000 g3icr: x?0fc46 thereafter, an interrupt occurs when the serial data is received. after specifying the interrupt group and vector, and clearing irfn, pro- gram the interrupt service routine.
121 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface 5-2-3 serial transmission/reception in i 2 c mode using timer 3 this section describes the example of serial interface 0 transmission/recep- tion in i 2 c mode explaining i 2 c start sequence transmission, data transmis- sion, data reception and i 2 c stop sequence transmission in order. pin setup set p70 pin and p72 pin to serial clock input and port input respectively. if p70 pin and p72 pin do not equip a pull-up resistor externally, set the pull-up resistor by the pull-up control register. [see chapter 8 ports] serial interface 0 setup (1) set the operating conditions to the serial 0 control register (sc0ctr). in i 2 c mode, select open-drain, 8-bit data transfer, msb as the bit order. in the system with the response from slave (ack), set parity bit to 1. (in the system without ack, select no parity.) select timer 3 underflow/16 as the clock source. 5 14 13 12 11 10 1 9876543210 0 c s n e t 0 c s n e r 0 c s e r b 0 c s s c 2 i 0 c s l t p 0 c s d o 0 c s m c 2 i 0 c s n l 0 c s 2 y t p 0 c s 1 y t p 0 c s 0 y t p 0 c s b s 0 c s d o p 0 c s 1 s 0 c s 0 s 1 1001 1111010111 sc0ctr: x?0fd80 (2) set the i 2 c sequence output bit of the serial 0 control register (sc0ctr) to 1. this makes the sbo pin output low and generates the start sequence. 5 14 13 12 11 10 1 9876543210 0 c s n e t 0 c s n e r 0 c s e r b 0 c s s c 2 i 0 c s l t p 0 c s d o 0 c s m c 2 i 0 c s n l 0 c s 2 y t p 0 c s 1 y t p 0 c s 0 y t p 0 c s b s 0 c s d o p 0 c s 1 s 0 c s 0 s 1 1011 1111010111 sc0ctr: x?0fd80 (3) load the data to the serial 0 transmit/receive register. this allows the data to output. the sbo pin output changes with 1/8 cycles delay of the falling edge of the sbt pin output. after transmission, both sbo pin output and sbt pin output stay low. set both the transmission enable flag and the reception enable flag to 1. in this example, select the slave re- sponse. when selecting p70 and p72 to i 2 c mode by the serial 0 control regis- ter, these pins becomes output mode. therefore, they should be set to in- put when they are used as ports.
122 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 5 serial interface (4) after transmission ends, read the dummy data of the serial 0 transmit/receive register (sc0trb). (5) read the serial 0 status register and verify the parity error. if a parity error occurs, the response is obtained from the slave correctly. if a parity error does not occur, the response is not obtained from the slave. (this step is not required in the sys- tem without ack.) when the data is transmitted continuously, repeat the steps (3) to (5). (6) load the dummy data x ff to the serial 0 transmit/receive register (sc0trb). this allows the sbo pin to output resistive high (because the sbo pin is an open- drain pin) and input low when the slave outputs low. (7) after reception ends, retrieve the received data by reading the serial 0 transmit/ receive register (sc0trb). when the data is received continuously, repeat the steps (6) and (7). (8) set the i 2 c sequence output bit of the serial 0 control register (sc0ctr) to 0. this makes the sbt pin output high and generates the stop sequence. 5 14 13 12 11 10 1 9876543210 0 c s n e t 0 c s n e r 0 c s e r b 0 c s s c 2 i 0 c s l t p 0 c s d o 0 c s m c 2 i 0 c s n l 0 c s 2 y t p 0 c s 1 y t p 0 c s 0 y t p 0 c s b s 0 c s d o p 0 c s 1 s 0 c s 0 s 1 1001 1111010101 sc0ctr: x?0fd80 (9) disable the reception enable flag once immediately after the stop sequence is generated. sbt pin output b7 b6 b5 b4 b3 b2 b1 b0 ack b7 b6 b5 b4 b3 b2 b1 b0 ack sbo pin output write to sc0trb register i c sequence output bit start detect bit = 1 stop detect bit = 1 transmitting the dummy data for reception transmit interrupt request transmit interrupt request (2) (3) (6) (8) 2 figure 5-2-3 transmission/reception in i 2 c mode an interrupt (a serial 0 transmission end interrupt or a serial 0 reception end interrupt) or polling the serial status register identifies the trans- mission end. (polling the reception state flag dur- ing i 2 c mode is prohibited.) an interrupt (a serial 0 transmission end interrupt or a serial 0 reception end interrupt) or polling the serial status register identifies the recep- tion end. (polling the reception state flag dur- ing i 2 c mode is prohibited.)
0 1 2 3 4 5 6 7 8 9 chapter 6 analog interface
124 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface 6-1 analog interface 6-1-1 overview this lsi series contains a 8-bit charge redistribution a/d converter. the a/ d converter supports digital signal processing in the voice and audio fre- quency ranges with a 8-bit resolution, a maximum conversion frequency of 208 khz (4.8 s per channel with a 20-mhz oscillator) and a low current. figure 6-1-1 analog interface configuration v dd an0 an1 an2 an3 an4 an5 an6 an7 v ss s/h 8-bit successive approximation adc a/dn conversion data buffer an0buf an1buf an2buf an3buf an4buf an5buf an6buf an7buf m u x notices when using a/d converter (1) set the impedance of the analog signal for a/d conversion to 8 k ? or less. (2) connect the a/d input pin to the condenser of 2000 pf or more to control the voltage change of the a/d input pin if the impedance of the analog signal cannot be set to 8 k ? or less. (3) to prevent the power potential fluctuation, do not change the chip output level from high level to low level or vice verse, or do not switch the peripheral load circuit on/off during a/d conversion. MN102L25X series r < 8 k ? or c 2000 pf equivalent circuit block outputs analog signal a/d input pin (avss) connect to vss in the chip model which has no avss. r c
125 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface table 6-1-2 a/d converter functions ?h?stands for channel. ann pin corresponds to the channel number. for example, the an3 pin corre- sponds to channel 3. e r u t a e fn o i t p i r c s e d h / sn i - t l i u b n o i s r e v n o c n o i t u l o s e r ) 0 n a o t 3 n a ( b s l 3 t i b - 8 ) 4 n a o t 7 n a ( b s l 4 t i b - 8 o t n i d e d i v i d s s v d n a d d v n e e w t e b e g a t l o v e h t s t r e v n o c r e t r e v n o c d / a e h t . f u b 0 n a o t f u b 7 n a n i d e r o t s i t l u s e r d e t r e v n o c s i h t d n a 6 5 2 e m i t n o i s r e v n o c ) r o t a l l i c s o z h m - 0 2 a h t i w s n 0 0 4 f o e m i t e l p m a s ( l e n n a h c r e p e r o m r o s 8 . 4 e c r u o s k c o l c8 , 4 , 2 , 1 y b d e d i v i d k l c s y s k c o l c m e t s y s l a n r e t n i e d o m g n i t a r e p o: s e d o m g n i t a r e p o 0 3 ) 7 l e n n a h c o t 0 l e n n a h c ( l e n n a h c e l g n i s f o n o i s r e v n o c e l g n i s , 2 l e n n a h c o t o l e n n a h c , 1 l e n n a h c o t 0 l e n n a h c ( s l e n n a h c e l p i t l u m f o n o i s r e v n o c e l g n i s l e n n a h c o t 0 l e n n a h c , 5 l e n n a h c o t 0 l e n n a h c , 4 l e n n a h c o t 0 l e n n a h c , 3 l e n n a h c o t 0 l e n n a h c ) 7 l e n n a h c o t 0 l e n n a h c , 6 ) 7 l e n n a h c o t 0 l e n n a h c ( l e n n a h c e l g n i s f o n o i s r e v n o c s u o u n i t n o c l e n n a h c o t o l e n n a h c , 1 l e n n a h c o t 0 l e n n a h c ( s l e n n a h c e l p i t l u m f o n o i s r e v n o c s u o u n i t n o c o t 0 l e n n a h c , 5 l e n n a h c o t 0 l e n n a h c , 4 l e n n a h c o t 0 l e n n a h c , 3 l e n n a h c o t 0 l e n n a h c , 2 ) 7 l e n n a h c o t 0 l e n n a h c , 6 l e n n a h c t r a t s n o i s r e v n o cg n i t t e s r e t s i g e r r o w o l f r e d n u 1 r e m i t t p u r r e t n i . s d n e e c n e u q e s n o i s r e v n o c e h t e m i t h c a e s r u c c o t p u r r e t n i n a selecting the a/d converter clock source the a/d converter clock source is selected to sysclk, sysclk/2, sysclk/4 or sysclk/8 as the conversion time is 4.8 s or more. select the a/d converter clock source as follows: sysclk frequency/divisor 5 mhz for example, select the a/d converter clock source as sysclk/4 (the conversion speed of 4.8 s) or sysclk/8 (the conversion time of 9.6 s) with a 20-mhz oscillator. select sysclk/2, sysclk/4 or sysclk/8 with a 10-mhz oscillator. select sysclk. sysclk/2, sysclk/4, sysclk/8 with a 5-mhz oscillator or less. the conversion time is 12 cycles of the a/d converter clock source as figure 6-1-2 shows. for example, the conversion time is calculated as follows when sysclk/4 is selected. [sysclk cycle (s) 4 (divisor) 12 (cycle)] state a/d conversion clock start s/h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 transfer figure 6-1-2 a/d conversion timing the input current is run to the stan- dard voltage only during conversion. therefore, the on/off control of in- put current to the voltage is not re- quired.
126 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface one channel/single conversion the a/d converter converts one a/d input signal of 1 channel once. an interrupt occurs as soon as the conversion ends. set the channel to be converted to an1ch[2:0] bits. set the antm1 flag and the anen flag to 0 and 1 respectively when the conversion starts using the anen flag. the anen flag becomes 1 during the conversion and 0 when the conversion ends. interrupt state anen ch n conversion figure 6-1-3 one channel/single conversion timing multiple channels/single conversion the a/d converter converts a/d input signals of continuous channels from channel 0 once. an interrupt occurs as soon as the conversion for all channels ends. set an1ch[2:0] bits to channel 0 and the annch flag to the last channel to be converted. set the antm1 flag and the anen flag to 0 and 1 respectively when the conversion starts using the anen flag. the anen flag becomes 1 during the conversion and 0 when the conversion sequence ends. in addition, the an1ch[2:0] bits are set to the channel number during the conversion and channel 0 after the conversion sequence ends. interrupt state anen ch0 conversion ch1 conversion ch2 conversion ch3 conversion ch4 conversion ch5 conversion figure 6-1-4 multiple channels/single conversion timing
127 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface one channel/continuous conversion the a/d converter converts one a/d input signal continuously. an interrupt occurs each time the conversion ends. set an1ch[2:0] bits to the channel number to be converted. set the antm1 flag and the anen flag to 0 and 1 respectively when the conversion starts using the anen flag. setting the anen flag to 0 ends the conversion forcibly. ch n conversion interrupt state anen ch n conversion ch n conversion figure 6-1-5 one channel/continuous conversion timing multiple channels/continuous conversion the a/d converter converts a/d input signals of continuous channels from channel 0 continuously. an interrupt occurs each time the continuous conversion ends. set an1ch[2:0] bits to channel 0 and the annch flag to the last channel to be converted. (the conversion starts from channel 0.) set the antm1 flag and the anen flag to 0 and 1 respectively when the conversion starts using the anen flag. the anen flag becomes 1 during the conversion and 0 when the conversion sequence ends. setting the anen flag to 0 ends the conversion forcibly. the an1ch[2:0] bits are set to the channel number during the conversion and channel 0 after the conversion sequence ends. interrupts state anen ch0 conversion ch1 conversion ch2 conversion ch0 conversion ch1 conversion ch2 conversion ch0 conversion figure 6-1-5 multiple channels/continuous conversion timing
128 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface 128 64 32 16 8 4 2 1 1 v dd v ss data bus anctr comp sysclk v dd v ss an7buf-an0buf an0 an1 an2 an3 an4 an5 an6 an7 m u x storage for data conversion shift registers for state information annch an1ch divider inc eight 8-bit registers figure 6-1-7 analog interface block diagram
129 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface 6-1-2 control registers the a/d converter contains the a/d conversion control register (anctr) and the a/d conversion data buffers (annbuf) corresponding to channel 7 to channel 0 (an7 pin to an0 pin). table 6-1-2 list of a/d conversion control registers the a/d conversion control register (anctr) sets the a/d conversion operating condi- tions. the a/d conversion results for channel 7 to channel 0 are input to the a/d conversion data buffers (annbuf). control register a/d conversion control register (anctr), x'00fda0' data buffers a/d0 conversion data buffer (an0buf), x'00fda8' a/d4 conversion data buffer (an4buf), x'00fdac8' a/d1 conversion data buffer (an1buf), x'00fda9' a/d5 conversion data buffer (an5buf), x'00fdad' a/d2 conversion data buffer (an2buf), x'00fdaa' a/d6 conversion data buffer (an6buf), x'00fdae' a/d3 conversion data buffer (an3buf), x'00fdab' a/d7 conversion data buffer (an7buf), x'00fdaf'
130 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface 6-2 analog interface setup examples 6-2-1 one channel a/d conversion using an2 pin this section describes the one channel a/d conversion setup by software. the an2 pin inputs the analog voltage (0 v to 5 v) and obtains the a/d conversion result. 5 v 0 v p96/an2 MN102L25X series 1000 pf figure 6-2-1 one channel a/d conversion pin setup (1) set an2 pin (p96) of the port 9 to input (p9dir6 = 0 ). a/d conversion control register setup (2) set the operating conditions to the a/d conversion control register (anctr). set anmd to 1ch/single conversion and select the clock source to sysclk/4 (10 mhz/4 with a 20-mhz oscillator). set anen to 0 and an1ch[2:0] to the chan- nel number to be converted. 5 14 13 12 11 10 1 9876543210 n a 2 h c n n a 1 h c n n a 0 h c n n a 2 h c 1 n a 1 h c 1 n a 0 h c 1 n a n e n a 1 m t n a 1 k c n a 0 k c n a 1 d m n a 0 d m 000 01000 1000 anctr: x?0fda0 annch[2:0] are ignored.
131 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface (3) set the anen flag to 1 to start the conversion. conversion starts on the falling edge of the a/d conversion clock source after anen is set to 1. the conversion time is 12 cycles of the a/d conversion clock source (4.8 s, 4.8 s to 5.2 s after anen is set). (4) wait for the conversion to end. set the anen flag to 1 during the conversion and 0 after the conversion ends. the program waits until the anen flag is cleared to 0. (5) read the a/d 2 conversion data buffer (an2buf). the converter divides 0 v to 5 v into 256 and the conversion result is the value from 0 to 255. 76543210 2 n a 7 f u b 2 n a 6 f u b 2 n a 5 f u b 2 n a 4 f u b 2 n a 3 f u b 2 n a 2 f u b 2 n a 1 f u b 2 n a 0 f u b an2buf: x?0fdaa set the anen flag to 1 when start- ing the conversion by software. the cpu can read the conversion re- sult by generating an interrupt. in this case, the cpu does not need to wait until the anen flag is set be- cause an interrupt occurs after the conversion result is stored in an2buf.
132 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface 6-2-2 multiple channels a/d conversion using an2 to an0 pins the an2, an1 and an0 pins input the analog voltage of 0 v to 5 v and obtains the a/d conversion results. the converter performs periodically using timer 1. volume 3 volume 2 0 5 10 volume 1 0 5 10 0 5 10 ch0 ch1 ch2 a/d conversion data buffers underflow timer 1 cpu mn102l(p, f) 25x series figure 6-2-2 multiple channel a/d conversion a/d conversion control register setup (2) set the operating conditions to the a/d conversion control register (anctr). set anmd to multiple channel/single conversion and select the anck[1:0] bits to sysclk/4 (10 mhz/4 with a 20-mhz oscillator). set anen and antm1 to 0 and 1 respectively. set an1ch[2:0] to the first channel number to be converted (channel 0) and annch[2:0] to the last channel number to be converted (channel 2). 5 14 13 12 11 10 1 9876543210 n a 2 h c n n a 1 h c n n a 0 h c n n a 2 h c 1 n a 1 h c 1 n a 0 h c 1 n a n e n a 1 m t n a 1 k c n a 0 k c n a 1 d m n a 0 d m 010 00001 1001 anctr: x?0fda0
133 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface timer 1 setup (2) set the timer 1 divisor. since timer 1 divides sysclk by 256, set the timer 1 base register (tm1br) to 255. (the valid range for tm1br is 1 to 255.) 76543210 1 m t 7 r b m t1 6 r b m t1 5 r b m t1 4 r b m t1 3 r b m t1 2 r b m t1 1 r b m t1 0 r b 11111111 tm1br: x?0fe11 (3) load the tm1br value to tm1bc. to do this, set tm1ld and tm1en to 1 and 0 resepctively. at the same time, select the clock source. 76543210 1 m t n e 1 m t d l m t1 s1 m t1 s0 01 10 tm1md: x?0fe21 (4) set both tm1ld and tm1en of the tm1md register to 0. (5) set tm1ld and tm1en to 0 and 1 respectively. this starts timer 1. counting starts at the beginning of the next cycle. when the timer 1 binary counter (tm1bc) reaches 0 and loads the value of 255 from the timer 1 base register (tm1br), a timer 1 underflow interrupt request occurs. the a/d converter converts each an2, an1, and an0 once when timer 1 underflows. if this setting is omitted, the timer 1 binary counter may not start at the first cycle. the periodical conversion saves the power consumption compared to the continuous conversion. underflow timer 1 ch0 ch1 ch2 conversion interrupt ch0 ch1 ch2 figure 6-2-3 a/d conversion timing (single conversion of channel 2 to channel 0) do not change the clock source af- ter this step. changing the clock source while controlling count op- eration will corrupt the binary counter value.
134 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 6 analog interface
0 1 2 3 4 5 6 7 8 9 chapter 7 atc
136 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 7 atc 7-1 atc 7-1-1 overview this series contains an auto transfer control (atc) which activates by an interrupt request. this series can transfer the data of serial interface 0 and internal ram speedily without using the cpu. table 7-1-1 atc functions the following is four serial interface 0 modes that the atc can operate. 1. synchronous transmission internal clock master (when this lsi se- ries generates the synchronous clock) 2. synchronous reception external clock master (when this lsi series receives the synchronous clock externally) 3. asynchronous transmission 4. asynchronous reception * setting bi-direction of transmission and reception does not allow. t r a t s t p u r r e t n i d n e n o i t p e c e r 0 l a i r e s r o t p u r r e t n i d n e n o i s s i m s n a r t 0 l a i r e s a n o i t c e r i d r e f s n a r tm a r l a n r e t n i ) b r t 0 c s ( r e f f u b e v i e c e r / t i m s n a r t 0 l a i r e s m a r l a n r e t n i e d o m r e f s n a r t * ) e t y b k 1 ( ' f f 3 e 0 0 ' x o t ' 0 0 0 e 0 0 ' x s i m a r l a n r e t n i r o f s s e r d d a e h t r e f s n a r t d r o w - e n o d n e r e f s n a r tg n i t t e s s s e r d d a m a r l a n r e t n i t i n u r e f s n a r te t y b d e e p s r e f s n a r t) r o t a l l i c s o z h m - 0 2 a h t i w ( e t y b / s n 0 0 6 g n i s s e r d d a r e f s n a r tt n e m e r c n i
137 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 7 atc serial interrupt serial interrupt atc transfer end interrupt (b) (a) atc transfer end interrupt service routine main program atc transfer interrupt service routine serial interrupt serial interrupt atc transfer end interrupt (b) (a) identify that both a serial interrupt and an atc transfer end interrupt occur. main program atc transfer interrupt service routine serial interrupt service routine serial interrupt (c) main program atc transfer interrupt service routine atc transfer end interrupt service routine serial interrupt atc transfer end interrupt a b internal ram sc0trb end address (atcend) c internal ram sc0trb end address (atcend) atcbc value the value of c is invalid. normal operations when a serial interrupt is enabled when a serial interrupt is disabled. when overrun error occurs figure 7-1-1 atc operations
138 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 7 atc the internal ram area where the atc can transfer the data is 1 k byte of x?0e000 to x?0e3ff? the upper 14 bits are fixed at ?0000000111000? therefore, the lower 10 bits are read when the atcbc counter is read. the address in the atcctr register or the atcbc counter is set to only lower 10 bits. 7-1-2 control registers the atc contains the atc control register (atcctr) and the atc binary counter (atcbc). r e t s i g e r l o r t n o c' 0 1 d f 0 0 ' x , ) r t c c t a ( r e t s i g e r l o r t n o c c t a r e t n u o c' 2 1 d f 0 0 ' x , ) c b c t a ( r e t n u o c y r a n i b c t a table 7-1-2 list of atc control registers the atc control register (atcctr) sets the transfer direction, the internal ram address for the atc end and atc enable. in addition, the atc monitors the overrun error (*) generation. overrun error * an overrun error occurs when a next serial 0 reception end interrupt occurs before the atc operation is completed after the serial 0 reception end interrupt occurred during the serial 0 reception (atcdir = 0 ). when this error occurs, setting bit 14 (ovref) of the atcctr register to 1 as well as negating bit 15 (atcen) ends the atc operation forc- ibly. at this point, the data stored in the address which subtracted by 1 from the internal ram address the atcbc counter shows is invalid. (no data is stored in the address the atcbc counter shows.) first, the atc binary counter (atcbc) sets the start address of internal ram. next the atcbc counter shows the ram address to write (or read) during atc operation. set the value of the internal ram address for atc end greater than the value of the atcbc counter.
139 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 7 atc 7-2 atc setup examples 7-2-1 serial reception the atc transfers the serial transmit/receive buffer contents to internal ram automatically after the serial reception is completed. the atc generates an atc transfer end interrupt after the atc transfers 5 times, and starts soft- ware processing. the start address of the atc destination is x 00e0a0 . serial interface 0 setup (1) enable an atc transfer end interrupt. 5 14 13 12 11 10 1 9876543210 6 g 2 v l 6 g 1 v l 6 g 0 v l c t a e i b 6 m t e i a 6 m t e i u 6 m t e i c t a r i b 6 m t r i a 6 m t r i u 6 m t r i c t a d i b 6 m t d i a 6 m t d i u 6 m t d i 000100000000000 g6icr: x?0fc40 5 14 13 12 11 10 1 9876543210 c b c t a 9 c b c t a 8 c b c t a 7 c b c t a 6 c b c t a 8 c b c t a 4 c b c t a 3 c b c t a 2 c b c t a 1 c b c t a 0 0010100000 atcbc: x?0fd12 (3) set the internal ram end address (x 00e0a4 ) and the transfer direction (serial internal ram) and clear the overrun error flag. atc setup (2) set the lower 10 bits of the internal ram start address for atc destination to the atc binary counter (atcbc). 5 14 13 12 11 10 1 9876543210 c t a n e r v o f e c t a r i d c t a 9 d n e c t a 8 d n e c t a 7 d n e c t a 6 d n e c t a 5 d n e c t a 4 d n e c t a 3 d n e c t a 2 d n e c t a 1 d n e c t a 0 d n e 00 0 0010100100 atcctr: x?0fd10 (4) set atcen to enable. keep the same setting as step (3). 5 14 13 12 11 10 1 9876543210 c t a n e r v o f e c t a r i d c t a 9 d n e c t a 8 d n e c t a 7 d n e c t a 6 d n e c t a 5 d n e c t a 4 d n e c t a 3 d n e c t a 2 d n e c t a 1 d n e c t a 0 d n e 10 0 0010100100 atcctr: x?0fd10 when a serial reception end inter- rupt is enabled, a serial reception end interrupt occurs each time the 1- word transfer ends.
140 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 7 atc (5) set the mode of serial interface 0. see 5-2 serial interface setup examples for detail. with the above setting, when the serial reception is completed, the atc transfer the re- ceived data to memory automatically. when the atc transfers repeatedly until the set number of operation is reached, an atc transfer end interrupt occurs and the atc transfer end interrupt service routine is executed. figure 7-2-1 serial reception data transfer a x'00e0a0' x'00e0a1' x'00e0a2' x'00e0a3' x'00e0a4' serial reception atc transfer d e b c d e destination memory a a b c a b c a b d c a b atc tranfer end interrupt processing transfer transfer transfer transfer transfer osci sysclk serial reception serial end interrupt address data bus authority atc transfer content cpu atc cpu start serial reception buffer end x'00fda8' cpu cpu internal ram write serial reception x'00e0a4' e cpu e cpu figure 7-2-2 last data transfer timing a, b, c, d and e means 1-byte data.
0 1 2 3 4 5 6 7 8 9 chapter 8 ports
142 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports 8-1 ports 8-1-1 overview this lsi series contains ten i/o ports. of ports 0 to 5, port 8 and port 9 are 8 bits. port 7 and port a are 6 bits. port 6 is 4 bits. all ports are bidirec- tional. port 0 and port 1 control the i/o direction in 8-bit unit. port 2 controls the i/o direction in 4-bit unit while ports 3 to a control the i/o direction in bit unit. table 8-1-1 port functions (1 of 8) port pin (shared pin) function port 0 is used as the port 0 general-purpose port, data (address/data separated) input/output, or address/data (address/data shared) input/output. at reset, this port operates as a general-pur- pose port input during other modes except processor mode and as d07 to d00 (ad07 to ad00) pins during processor mode. however, this port operates as a general-purpose port during processor mode when 8-bit bus width is selected for all spaces in address/data separated mode. the mode for port 0 is selected in 8-bit unit. during processor mode (without 8-bit bus width setting for all spaces), p0md is invalid. during memory expansion mode, set p0md and p0dir to 1 and 0 respectively. p07 to 00 (d07 to 00) (ad07 to 00) p0dir0 dlp address/data output control (bus controller) p0out7 to 0 address/data output (bus controller) p0in7 to 0 data input (bus controller) 0 1 mux p0md0 port 0 p07 to p00 (d07 to d00) (ad07 to ad00)
143 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports table 8-1-1 port functions (2 of 8) port pin (shared pin) function port 1 is used as the port 1 general-purpose port, data (address/data separated) input/output, or address/data (address/data shared) input/output. at reset, this port operates as a general-pur- pose port input during other modes except processor mode and as d15 to d08 (ad15 to ad08) pins during processor mode. the mode for port 1 (either port, data or address/data mode) is selected in 8-bit unit. during processor mode (without 8-bit bus width setting for all spaces), p1md is invalid. during memory expansion mode, set p1md and p1dir to 1 and 0 respectively. p17 to 10 (ad15 to 08) p1dir0 dhp address/data output control (bus controller) p1out7 to 0 address/data (bus controller) p1in7 to 0 data input (bus controller) 0 1 mux p1md0 port 1 p17 to p10 (d15 to d08) (ad15 to ad08) port 2 is used as the port 2 general-purpose port or address output. at reset, this port operates as a general-purpose port input during other modes except processor mode and as a07 to a00 pins during processor mode. during processor mode, p2md is invalid. see ?-2-1 memory expansion mode (address/data separated mode)?and ?-2-3 memory expansion mode (ad- dress/data shared mode)? for port setting during memory expansion mode. p27 to 24 (a07 to04) p23 to 20 (a03 to 00) p2dir4,p2dir0 alp address/data output control (bus controller) p2out7 to 0 address/data output control (bus controller) p2in7 to 0 0 1 mux p2md4,p2md0 port 2 p27 to p20 (a07 to a00)
144 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports table 8-1-1 port functions (3 of 8) port pin (shared pin) function port 3 is used as the port 3 general-purpose port or address output. at reset, this port operates as a general-purpose port input during other modes except processor mode and as a15 to a08 pins during processor mode. during processor mode, p3md is invalid. see ?-2-1 memory expansion mode (address/data separated mode)?and ?-2-3 memory expansion mode (ad- dress/data shared mode)? for port setting during memory expansion mode. p37 to 30 (a15 to 08) p3dir7 to 0 amp address/data output control (bus controller) p3out7 to 0 address/data (bus controller) p3in7 to 0 0 1 mux p3md7 to 0 port 3 p37 to p30 (a15 to a08) port 4 is used as the port 4 general-purpose port, address output, a/d converter input pin or cpu status signal pin. at reset, this port operates as a general-purpose port input during other modes except processor mode and as a21 to a16 pins (p47 and p46 operate as general-pur- pose input) during processor mode. during processor mode, p4md of p45 to p40 is invalid. see ?-2-1 memory expansion mode (address/data separated mode)?and ?-2-3 memory expansion mode (address/data shared mode)? for port setting during memory expansion mode. p43 to 40 (a19 to 16) p4dir3 to 0 amp address/data output control (bus controller) p4out3 to 0 address/data (bus controller) p4in3 to 0 0 1 mux p4md3 to 0 port 4 p43 to p40 (a19 to a16) p45 to p44 (a21 to a20, an5 to an4) p46 (a22, an6, stop) p47 (a23, an7, wdout)
145 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports table 8-1-1 port functions (4 of 8) port pin (shared pin) function p45 to 44 (a21 to 20) (an5 to 4) p4dir5 to 4 address/data output control (bus controller) p4out5 to 4 p4in5 to 4 0 1 mux p4md5 to 4 address to a/d converter ahp port 4 p47 to 46 (a23 to 22) (an7 to 6) (wdout,stop) p6md7 to 6 p4dir7 to 6 p4out7 to 6 address watchdog overflow,stop p4md7 to 6 ab (a , b) 0 * 1 0 1 1 to a/d converter p4in7 to 6 ahp address/data output control (bus controller)
146 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports table 8-1-1 port functions (5 of 8) port pin (shared pin) function port 5 is used as the port 5 general-purpose port or external memory interface signals pins (/ word, /bstre, ale, /ale, /brack, /breq, /cs3 to /cs0). at reset, this port operates as a general-purpose port input during other modes except processor mode while p56, p53 to p50 pins operate as /bstre, ale, /ale, /brack, /breq, /cs3 to /cs0 pins during proces- sor mode. during processor mode, p5md6, p5md3 to p5md0 are invalid. p57 to 50 (word,cs3 to 0 bstre/ale/ale) 0 1 mux p57,p55,p54do not contain pull-up resistors. p5dir7 to 0 bifp1 to 0 external memory interface signal output control (bus controller) p5out7 to 0 external memory interface signal (bus controller) p5in7 to 0 (word,breq) ( bus controller ) p5md6 to 0 p57 does not have mux. port 5 p57 to p50 (/word, /bstre, ale, /ale, /brack, /breq, /cs3 to /cs0) port 6 is used as the port 6 general-purpose port or external memory interface signals pins (wait, /re, /weh, /wel). at reset, this port operates as a general-purpose port input during other modes except processor mode while p63 to p61 pins operate as /weh, /wel and /re pins during processor mode. during processor mode, p6md3 to p6md1 are invalid. p63 to 60 (weh,wel, re,wait) 0 1 mux p6dir3 to 0 bifp0,waitp external memory interface signal output control (bus controller) p6out3 to 0 external memory interface signal (bus controller) p6in3 to 0 wait ( bus controller ) p6md3 to 0 p60 does not have mux. port 6 p63 to p60 (/wel, /weh, /re, wait)
147 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports table 8-1-1 port functions (6 of 8) port pin (shared pin) function port 7 is used as the port 7 general-purpose port or serial interface signal pins. at reset, this port operates as a general-purpose port input. p75 (sbo1) p72 (sbo0) sb1p,sb0p p7in5,p7in2 0 1 mux p7dir4,p7dir1 sb1p,sb0p p7out4,p7out1 p7in4,p7in1 p74 (sbi1) p71 (sbi0) p73 (sbt1) p70 (sbt0)) p7md3,p7md0 sb1p,sb0p serial i/f clock input (note) c=a*b a decoder(note) c p7in3,p7in0 serial i/f clock output p7out3,p7out0 p7dir3,p7dir0 serial i/f clock enable serial i/f data output p7out5,p7out2 p7dir5,p7dir2 p7md5,p7md2 b serial i/f data input 0 1 mux a serial i/f data enable port 7 p75 (sbo1) p74 (sbi1) p73 (sbt1) p72 (sbo0) p71 (sbi0) p70 (sbt0)
148 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports table 8-1-1 port functions (7 of 8) port pin (shared pin) function port 8 is used as the port 8 general-purpose port or timer input/output pins (tm0io to tm5io, tm6ioa, tm6iob). at reset, this port operates as a general-purpose port input. p87 (tm6iob) p86 (tm6ioa) p85 to 80(tm5io to tm0io) p8dir7 to 0 p8out7 to 0 timer output p8in7 to 0 timer input 0 1 mux p8md7 to 0 port 8 p87 (tm6iob) p86 (tm6ioa) p85 to p80 (tm5io to tm0io) port 9 is used as the port 9 general-purpose port, timer input/output pins or a/d converter input pins (an3 to an0, tm7ic, tm7iob, tm7ioa, tm6ic). at reset, this port operates as a general-purpose port input. p93 (tm7ic) p92 (tm7iob) p91 (tm7ioa) p90 (tm6ic) p9dir3 to 0 p9out3 to 0 timer output p9in3 to 0 timer input 0 1 mux p9md2,p9md1 p93 and p90do not have mux. port 9 p97 to p94 (an3 to an0) p93 (tm7ic) p92 (tm7iob) p91 (tm7ioa) p90 (tm6ic) p97 (an3) p96 (an2) p95 (an1) p94 (an0) p9dir7 to 4 p9out7 to 4 p9in7 to 4 to a/d converter
149 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports table 8-1-1 port functions (8 of 8) port pin (shared pin) function port a is used as the port a general-purpose port or interrupt related signal pins (adsep, irq4 to irq0). at reset, this port operates as a general-purpose port input. this port can read the level of /nmi pin by operating as the port input pin (pain6), and verify an error due to chatter- ing using software. pa5 (adsep) pa4 to 0 (irq4 to 0) padir5 to 0 pa4p,pa3p,pa2p, pa1p,pa0p paout5 to 0 pain5 to 0 (irq4 to 0) adsep nmi pain6 nmi pa4 does not have a pull-up resistor. port a pa5 (adsep) pa4 to pa0 (irq4 to irq0)
150 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports 8-1-2 control registers this section describes the port control registers. 0 t r o p r e t s i g e r t u p t u o 0 t r o p r e t s i g e r t u p n i 0 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 0 t r o p r e t s i g e r e d o m t u p t u o 0 t r o p t u o 0 p n i 0 p r i d 0 p d m 0 p ' 0 c f f 0 0 ' x ' 0 d f f 0 0 ' x ' 0 e f f 0 0 ' x ' 0 f f f 0 0 ' x 1 t r o p r e t s i g e r t u p t u o 1 t r o p r e t s i g e r t u p n i 1 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 1 t r o p r e t s i g e r e d o m t u p t u o 1 t r o p t u o 1 p n i 1 p r i d 1 p d m 1 p ' 1 c f f 0 0 ' x ' 1 d f f 0 0 ' x ' 1 e f f 0 0 ' x ' 1 f f f 0 0 ' x 2 t r o p r e t s i g e r t u p t u o 2 t r o p r e t s i g e r t u p n i 2 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 2 t r o p r e t s i g e r e d o m t u p t u o 2 t r o p t u o 2 p n i 2 p r i d 2 p d m 2 p ' 2 c f f 0 0 ' x ' 2 d f f 0 0 ' x ' 2 e f f 0 0 ' x ' 2 f f f 0 0 ' x 3 t r o p r e t s i g e r t u p t u o 3 t r o p r e t s i g e r t u p n i 3 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 3 t r o p r e t s i g e r e d o m t u p t u o 3 t r o p t u o 3 p n i 3 p r i d 3 p d m 3 p ' 3 c f f 0 0 ' x ' 3 d f f 0 0 ' x ' 3 e f f 0 0 ' x ' 3 f f f 0 0 ' x 4 t r o p r e t s i g e r t u p t u o 4 t r o p r e t s i g e r t u p n i 4 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 4 t r o p r e t s i g e r e d o m t u p t u o 4 t r o p t u o 4 p n i 4 p r i d 4 p d m 4 p ' 4 c f f 0 0 ' x ' 4 d f f 0 0 ' x ' 4 e f f 0 0 ' x ' 4 f f f 0 0 ' x 5 t r o p r e t s i g e r t u p t u o 5 t r o p r e t s i g e r t u p n i 5 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 5 t r o p r e t s i g e r e d o m t u p t u o 5 t r o p t u o 5 p n i 5 p r i d 5 p d m 5 p ' 5 c f f 0 0 ' x ' 5 d f f 0 0 ' x ' 5 e f f 0 0 ' x ' 5 f f f 0 0 ' x 6 t r o p r e t s i g e r t u p t u o 6 t r o p r e t s i g e r t u p n i 6 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 6 t r o p r e t s i g e r e d o m t u p t u o 6 t r o p t u o 6 p n i 6 p r i d 6 p d m 6 p ' 6 c f f 0 0 ' x ' 6 d f f 0 0 ' x ' 6 e f f 0 0 ' x ' 6 f f f 0 0 ' x 7 t r o p r e t s i g e r t u p t u o 7 t r o p r e t s i g e r t u p n i 7 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 7 t r o p r e t s i g e r e d o m t u p t u o 7 t r o p t u o 7 p n i 7 p r i d 7 p d m 7 p ' 7 c f f 0 0 ' x ' 7 d f f 0 0 ' x ' 7 e f f 0 0 ' x ' 7 f f f 0 0 ' x table 8-1-2 list of port control registers
151 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports 8 t r o p r e t s i g e r t u p t u o 8 t r o p r e t s i g e r t u p n i 8 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 8 t r o p r e t s i g e r e d o m t u p t u o 8 t r o p t u o 8 p n i 8 p r i d 8 p d m 8 p ' 8 c f f 0 0 ' x ' 8 d f f 0 0 ' x ' 8 e f f 0 0 ' x ' 8 f f f 0 0 ' x 9 t r o p r e t s i g e r t u p t u o 9 t r o p r e t s i g e r t u p n i 9 t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i 9 t r o p r e t s i g e r e d o m t u p t u o 9 t r o p t u o 9 p n i 9 p r i d 9 p d m 9 p ' 9 c f f 0 0 ' x ' 9 d f f 0 0 ' x ' 9 e f f 0 0 ' x ' 9 f f f 0 0 ' x a t r o p r e t s i g e r t u p t u o a t r o p r e t s i g e r t u p n i a t r o p r e t s i g e r l o r t n o c t u p t u o / t u p n i a t r o p t u o a p n i a p r i d a p ' a c f f 0 0 ' x ' a d f f 0 0 ' x ' a e f f 0 0 ' x r e h t o r e t s i g e r l o r t n o c p u - l l u p t r o p r e t s i g e r p a w s e t y b a t a d d r o w l r e t s i g e r p a w s e t y b a t a d r e t n i o p h r e t s i g e r p a w s e t y b a t a d r e t n i o p l r e t s i g e r p a w s e t y b a t a d d r o w - g n o l h r e t s i g e r p a w s e t y b a t a d d r o w - g n o l u l p p p w s b w l p w s b p h p w s b p l p w s b l h p w s b l ' 0 b f f 0 0 ' x ' 0 a f f 0 0 ' x ' 2 a f f 0 0 ' x ' 4 a f f 0 0 ' x ' 6 a f f 0 0 ' x ' 8 a f f 0 0 ' x
152 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports the port output register (pnout) sets the data to be output. the port input register (pnin) reads the pin values. the port input/output control register (pndir) sets the input or output of all bits or each bit. the output mode register (pnmd) selects the port output. the port pull-up control register (pplu) selects on/off of each pin. selection p0dir0 p0md0 description port input select the port input or the port output only when 8-bit bus width for all spaces is selected during single-chip mode or address/data separated mode (the word pin is high and all 8th bits of the memmd3 to memmd1 registers are high). port output d07 to d00/ ad07 to ad00 reserved 0 0 1 0 1 1 select d07 to d00 during address/data separated mode, ad07 to ad00 during ad- dress/data shared mode. p07 to p00 pins note: set only in 8-bit unit. selection p1dir0 p1md0 description port input select the port input or the port output only when single-chip mode is selected. port output d15 to d08/ ad15 to ad08 reserved 0 0 1 0 0 1 1 1 select d15 to d08 during address/data separated mode, ad15 to ad08 during ad- dress/data shared mode. p17 to p10 pins note: set only in 8-bit unit. 0 1 selection p2dir0 p2md0 description port input do not select the port input or the port output in address/data separated mode during processor mode. port output a03 to a00 reserved 0 0 1 0 0 1 1 1 p23 to p20 pins note: set only in 4-bit unit. selection p2dir4 p2md4 description port input do not select the port input or the port output in address/data separated mode during processor mode. port output a07 to a04 reserved 0 0 1 0 0 1 1 1 p27 to p24 pins note: set only in 4-bit unit. the pullup resistor is approximately 30 k ? . see the product specifica- tions for the exact value.
153 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports selection p3dirn (n=7 to 0) p3mdn (n=7 to 0) description port input do not select the port input or the port output in address/data separated mode during processor mode. port output a15 to a08 reserved 0 0 1 0 0 1 p37 to p30 pins 1 1 selection p4dirn (n=3 to 0) p4mdn (n=3 to 0) description port input do not select the port input or the port output during processor mode. port output a19 to a16 reserved 0 0 1 0 0 1 p43 to p40 pins 1 1 selection p4dirn (n=5, 4) p4mdn (n=5, 4) description port input do not select the port input or the port output during processor mode. port output a21, a20 reserved 0 0 1 0 0 1 p45 to p44 pins 1 1 an5, 4 input selection p4dir6 p4md6 port input port output a22 output stop output 0 0 * p46 pin an6 input reserved 1 0 * 0 1 0 1 1 1 1 1 0 p6md6
154 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports selection p4dir7 p4md7 port input port output a23 output wdout output 0 0 * p47 pin an7 input reserved 1 0 * 0 1 0 1 1 1 1 1 0 p6md7 selection p5dirn (n=3 to 0) p5mdn (n=3 to 0) description port input do not select the port input or the port output during processor mode. port output /cs output reserved 0 0 1 0 0 1 p53 to p50 pins 1 1 selection p5dir4 p5md4 port input port output /breq output reserved 0 0 1 0 0 1 1 1 p54 pin selection p5dir5 p5md5 port input port output /breq output reserved 0 0 1 0 1 1 0 1 p55 pin selection p5dir6 p5md6 description port input do not select the port input or the port output during processor mode. port output /bstre, ale, /ale reserved 0 0 1 0 0 1 1 1 select /bstre during address/data separated mode, ale (/ale) during address/ data shared mode. p56 pin selection p5dir7 description port input select the port input during single-chip mode. otherwise, select /word input. /word input port output 0 1 p57 pin
155 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports selection p6dir0 description port input select wait input when the clock is set to handshake mode. otherwise, select the port input. wait input port output 0 1 p60 pin selection p6dirn (n=3 to 1) p6mdn (n=3 to 1) description port input do not select the port input or the port output during processor mode. port output /weh, /wel. /re output reserved 0 0 1 0 0 1 p63 to p61 pins 1 1 selection p7dirn (n=3,0) p7mdn (n=3,0) description port input serial clock input operate as a serial clock input pin when setting the serial clock source to the sbt pin (including i 2 c mode). serial clock i/o (half-duplex) port output serial clock output 1 0 0 1 p73 and p70 pins 1 1 0 0 become output only when this lsi series output during bidirectional synchronous transfer. selection p7dirn (n=4, 1) description port input serial input operate as a serial data input pin when the serial reception is enabled. port output 0 1 p74 and p71 pins selection p7dirn (n=5, 2) p7mdn (n=5, 2) description port input select the port input during i 2 c mode. port output serial output 0 * 1 0 1 1 p75 and p72 pins
156 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports selection p8dirn (n=7 to 0) p8mdn (n=7 to 0) description port input operate as a timer input pin when selecting the timer closk source to the pin. timer input port output timer output 0 * 1 0 p87 to p80 pins 1 1 selection p9dirn (n=3, 0) description port input serial input operate as a serial data input pin when selecting the 16-bit timer binary counter clear condition 2 (5th bit of tmnmd). port output 0 1 p93 and p90 pins selection p9dirn (n=2, 1) p9mdn (n=2, 1) description port input operate as a timer input pin when setting the timer closk source, capture, trigger and encoder. timer input port output timer output 0 * 1 0 p92 and p91 pins 1 1 selection p9dirn (n=7 to 4) port output 0 1 p97 to p94 pins port input an3 to 0 input selection padirn (n=4 to 0) port output 0 1 pa4 to pa0 pins port input interrupt input
157 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports selection padir5 description port input operate as the port input only during single-chip mode. otherwise, operate as the adsep input. adsep input port output 0 1 pa5 pin operate as the port output only during single-chip mode. this operation is not guaranteed with other modes.
158 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports 8-2 byte swap registers 8-2-1 overview this lsi series contains a word byte swap register, point byte swap registers and long word swap registers. the data is swapped and read as figure 8-2-1 shows. ab bp15 8 7 0 word byte swap register wbswp(x'00ffa0') (all initial values are 0.) ba ab c bp23 16 7 0 15 8 ab c cb a d dc b a write read write read write read long-word byte swap register lbswph(x'00ffa8') lbswpl(x'00ffa6') (all initial values are 0.) 23 16 7 0 15 8 bp31 24 point byte swap register pbswph(x'00ffa4') pbswpl(x'00ffa2') (all initial values are 0.) figure 8-2-1 byte swap register
159 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports 8-3 pull-up control register 8-3-1 overview this lsi series contains a pin which sets a pull-up resistor using the pro- gram. see 9-2-3 list of pin functions . t i b d e d n o p s e r r o c r e b m u n n i p n o i t p i r c s e d 0 1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1 4 1 5 1 1 9 o t 4 8 0 0 1 o t 3 9 9 2 o t 6 2 , 6 1 o t 3 1 8 3 o t 5 3 , 3 3 o t 0 3 7 4 o t 4 4 , 2 4 o t 9 3 1 1 1 , 4 o t 2 8 o t 5 6 7 7 7 8 7 9 7 0 8 9 6 o t 7 6 2 7 o t 0 7 d e v r e s e r 0 0 p o t 7 0 p , 0 0 d a o t 7 0 d a , 0 0 d o t 7 0 d 1 1 p o t 7 1 p , 8 0 d a o t 5 1 d a , 8 0 d o t 5 1 d 0 2 p o t 7 2 p , 0 0 a o t 7 0 a 0 3 p o t 7 3 p , 8 0 a o t 5 1 a 0 4 p o t 7 4 p , 6 1 a o t 3 2 a 0 6 p , t i a w 6 5 p , 1 6 p o t 3 6 p , e r t s b / , l e w / , h e w / , e r / 0 5 p o t 3 5 p , 0 s c / o t 3 s c / 0 a p , 0 q r i / 1 a p , 1 q r i / 2 a p , 2 q r i / 3 a p , 3 q r i / 4 a p , 4 q r i / 0 7 p o t 2 7 p , 0 o b s , 0 i b s , 0 t b s 3 7 p o t 5 7 p , 1 o b s , 1 i b s , 1 t b s . 0 o t t e s s y a w l a table 8-3-1 pull-up control register
160 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 8 ports
0 1 2 3 4 5 6 7 8 9 chapter 9 appendix
162 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-1 electrical characteristics 9-1-1 electrical characteristics 5 v structure cmos integrated circuit application general purpose function 16-bit microcontroller pin configuration figure 1-4-1 external dimensions figure 1-5-1 a. absolute maximum ratings v ss = 0 v parameter symbol rating unit a1 power supply voltage v dd - 0.3 to + 7.0 v a2 input pin voltage v i - 0.3 to v dd + 0.3 v a3 output pin voltage v o - 0.3 to v dd + 0.3 v a4 input/output pin voltage v io - 0.3 to v dd + 0.3 v a5 operating ambient temperature topr - 40 to + 85 c a6 storage temperature tstg -55 to + 125 c note: 1. absolute maximum ratings are stress ratings not to cause damage to the device. operation at these ratings is not guaranteed. 2. all of the v dd and vss pins are external pins. connect them directly to the power source and ground. 3. to prevent latch-up tolerance, connect more than one by-pass condenser between power supply pins and ground. use at least 0.2 f condenser.
163 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix b. operating conditions v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max b1 power supply voltage v dd 4.5 5 5.5 v crystal oscillator 1 (osci) b2 oscillator frequency f osc 1 420 mhz crystal oscillator 2 (xi) b3 oscillator frequency f osc 2 32 200 khz
164 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 5.0 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max c1 power supply current during operation i dd 1 v i = v dd or v ss f osc 1 = 20 mhz output pins open 75 ma c2 power supply current during slow mode i dd 2 v i = v dd or v ss f osc 2 = 32 khz output pins open 10 ma c3 power supply current in stop mode i dd 3 oscillator stop all functions stop 50 a c4 power supply current in halt0 mode i dd 4 fosc1 = 20 mhz fosc2 = 32 khz 30 ma c5 power supply current in halt1 mode i dd 5 fosc1 = oscillator stop fosc2 = 32 khz 1 ma
165 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max input/output pins 1 < output pushpull/input cmos level schmidt trigger > tmnio(n=0 to 5), tmnioa(n=6, 7), tmniob(n=6, 7), tmnic(n=6, 7), adsep c6 input high voltage v ih1 v dd ? 0.8 v v il1 only adsep pin v dd ? 0.1 v v il2 other pins v dd ? 0.2 v c8 output high voltage v oh1 v dd = 5.0 v i oh = -4.0 ma v dd -0.6 v c9 output low voltage v ol1 v dd = 5.0 v i ol = 4.0 ma 0.4 v c10 output leakage current i lo1 vo = hi-z +/- 10 a input/output pins 2 < output pushpull/input cmos level schmidt trigger/programmable pullup > sbo1, sbi1, sbt1, sbo0, sbi0, sbt0 c11 input high voltage v ih2 v dd ? 0.8 v c12 input low voltage v il3 v dd ? 0.2 v c13 output high voltage v oh2 v dd = 5.0 v i oh = -4.0 ma v dd -0.6 v c14 output low voltage v ol2 v dd = 5.0 v i ol = 4.0 ma 0.4 v c15 output leakage current i lo2 vo = hi-z +/- 10 a c16 pullup resistance p pu1 v dd = 5.0 v v i = 1.5 v 10 30 50 k ? input low voltage c7
166 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max input/output pins 3 < output pushpull/input ttl level schmidt trigger/programmable pullup > wait, /re, /wel, /weh, /cs3 to /cs0, ale, a19 to a0, /irq4 to /irq0 c17 input high voltage v ih3 2.4 v c18 input low voltage v il4 0.8 v c19 output high voltage v oh3 v dd = 5.0 v i oh = -2.0 ma v dd -0.6 v c20 output low voltage v ol3 v dd = 5.0 v i ol = 4.0 ma 0.4 v c21 output leakage current i lo3 vo = hi-z +/- 10 a c22 pullup resistance p pu2 v dd = 5.0 v v i = 1.5 v 10 30 50 k ? input/output pins 4 < output pushpull/input ttl level schmidt trigger > /breq, /brack, /word c23 input high voltage v ih4 2.4 v c24 input low voltage v il5 0.8 v c25 output high voltage v oh4 v dd = 5.0 v i oh = -2.0 ma v dd -0.6 v c26 output low voltage v ol4 v dd = 5.0 v i ol = 4.0 ma 0.4 v c27 output leakage current i lo4 vo = hi-z +/- 10 a
167 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max input/output pins 5 < output pushpull/input ttl level schmidt trigger/programmable pullup > d15 to d0 c28 input high voltage v ih5 2.4 v c29 input low voltage v il6 0.8 v c30 output high voltage v oh5 v dd = 5.0 v i oh = -2.0 ma v dd -0.6 v c31 output low voltage v ol5 v dd = 5.0 v i ol = 4.0 ma 0.4 v c32 output leakage current i lo5 vo = hi-z +/- 10 a c33 pullup resistance p pu3 v dd = 5.0 v v i = 1.5 v 10 30 50 k ? input/output pins 6 < output pushpull/analog input > an3 to an0 c34 input high voltage v ih6 v dd ? 0.8 v c35 input low voltage v il7 v dd ? 0.2 v c36 output high voltage v oh6 v dd = 5.0 v i oh = -4.0 ma v dd -0.6 v c37 output low voltage v ol6 v dd = 5.0 v i ol = 4.0 ma 0.4 v c38 output leakage current i lo6 vo = hi-z +/- 10 a
168 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max input/output pins 7 < output pushpull/analog input/programmable pullup > a23 to a20 c39 input high voltage v ih7 v dd ? 0.8 v c40 input low voltage v il8 v dd ? 0.2 v c41 output high voltage v oh7 v dd = 5.0 v i oh = -4.0 ma v dd -0.6 v c42 output low voltage v ol7 v dd = 5.0 v i ol = 4.0 ma 0.4 v c43 output leakage current i lo7 vo = hi-z +/- 10 a c44 pullup resistance p pu4 v dd = 5.0 v v i = 1.5 v 10 30 50 k ? input/output pins 8 < input cmos level schmidt trigger/output open-drain/pullup > /rst c45 input high voltage v ih8 v dd ? 0.9 v c46 input low voltage v il9 v dd ? 0.1 v c47 pullup resistance p pu5 v dd = 5.0 v v i = 1.5 v 10 30 50 k ?
169 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol c onditions unit min typ max output pin < output pushpull > sysclk c48 output high voltage v oh8 v dd = 5.0 v i oh = -4.0 ma v dd -0.6 v c49 output low voltage vo l8 v dd = 5.0 v i ol = 4.0 ma 0.4 v input pins < input cmos level schmidt trigger > /nmi, mode c50 input high voltage v ih9 v dd ? 0.9 v c51 input low voltage v il10 v dd ? 0.1 v c52 input leakage current v lo9 v dd = 5.5 v v i = v ss to v dd +/- 10 a osci pin, xi pin (at external clock input) : crystal, ceramic self-excited oscillation see figure 1-4-2 to figure 1-4-3 c53 input high voltage v ih10 v dd ? 0.8 v dd v c54 input low voltage v il11 v ss v dd ? 0.2 v pin capacitance c55 input pin c in 715 pf c56 output pin c out v in = 0 v ta=25 c 715 pf c57 input/output pin c i/o 715 pf
170 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix d. a/d converter characteristics v dd = 5.0 v v ss = 0 v ta = 25 c capacitance parameter sy mbol conditions unit min typ max d1 resolution 8 bits +/- 3 lsb +/- 3 lsb d3 a/d conversion time fosc = 20 mhz 4.8 s d4 a/d conversion cycle fosc = 20 mhz 4.8 s d5 analog input voltage v ia v ss v dd v a/d conversion relative precision v dd = 5 v v ss = 0 v an3-0 an7-4 d2
171 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix e. ac characteristics v dd = 4.5 v to 5.5 v in p ut timin g conditions v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max external clock input timing (fosc1 = 20 mhz) e1 external clock input cycle time t exccyc 50 ns e2 external clock input high pulse width t exch -5 ns e3 external clock input low pulse width t excl fig 9-1 -5 ns e4 external clock input rise time t excr 5 ns e5 external clock input fall time t excf 5 ns reset input timing e6 reset signal pulse width (/rst) t rstw fig 9-2 4 t exccyc t ex ccy 2 t ex ccy 2
172 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v in p ut timin g conditions v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max data transfer signal input timing e7 data acknowledge signal setup time (wait) t waits fi g 9-4 20 ns e8 data acknowledge signal hold time (wait) t waith fig 9-6 0 ns data transfer signal input timing e9 read data setup time (d15-00) t rds fig 9-3 fi g 9-4 20 ns e10 read data hold time (d15-00) t rdh fig 9-5 fig 9-6 0 ns bus authority request input timing e11 bus authority request signal setup time (/breq) t breqs fi g 9-8 0 ns e12 bus authority request signal hold time (/breq) t breqh 0 ns interrupt signal input timing e13 nonmaskable interrupt signal pulse width (nmi) t nmiw fi g 9-9 5 (note) t cyc e14 external interrupt signal pulse width (/irq4-0) t irqw 2 (note) t cyc note : an interru p t ma y occur when the noise of the s p ecified time or less is in p ut.
173 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v in p ut timin g conditions v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol c onditions unit min typ max serial interface related signal timing (synchronous serial reception) e15 data reception setup time (sbi1-0) t rxds 25 ns e16 data reception hold time (sbi1-0) t rxdh fi g 9-13 25 ns e17 serial clock input high pulse width (sbt1-0) t sch t cyc+100 ns e18 serial clock input low pulse width (sbt1-0) t scl t cyc+100 ns timer/counter signal input timing e19 timer external input clock low pulse width (tmnio: n=5-0) (tmnioa, tmniob, tmnic: n=6,7) t tcclkl fi g 9-14 t cyc ns e20 timer external input clock high pulse width (tmnio: n=5-0) (tmnioa, tmniob, tmnic: n=6,7) t tcclkh t cyc ns
174 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix f. ac characteristics (output) v dd = 4.5 v to 5.5 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max system clock output timing f1 system clock output cycle time (sysclk) t cyc 100 ns f2 system clock output low pulse width (sysclk) t cl 45 ns f3 system clock output high pulse width (sysclk) t ch fig 9-1 35 ns f4 system clock output rise time (sysclk) t cr 10 ns f5 system clock output fall time (sysclk) t cf 10 ns
175 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max data transfer signal output timing 1 f6 address delay time 1 (a23-0), (a23-16) t ad1 fig 9-3 to fig 9-6 30 ns f7 address delay time 2 (ad15-0) t ad2 fig 9-4 fig 9-6 +15 ns f8 address hold time 1 (a23-0), (a23-16) t ah1 fig 9-3 fig 9-4 5 ns f9 address hold time 2 (a23-0), (a23-16) t ah2 fig 9-5 fig 9-6 ns f10 address hold time 3 (ad15-0) t ah3 -10 ns f11 address/data hold time 1 (ad15-0) t adh1 fig 9-5 fig 9-6 5 ns f12 address/data hold time 2 (ad15-0) t adh2 ns f13 data delay time 1 (d15-0) t dd1 fig 9-3 fig 9-4 15 ns f14 data delay time 2 (ad15-0) t dd2 fig 9-5 fig 9-6 ns f15 data delay time 3 (d15-0) t dd3 fig 9-7 ns f16 data hold time 1 (d15-0) t dh1 fi g 9-3 5 ns f17 data hold time 2 (d15-0) t dh2 fig 9-4 ns t c y 4 t c y 4 t cyc 4 t c y 4 t cyc 4 t cyc 2 t cyc 4 t c y c 4
176 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max data transfer signal output timing 2 f18 chip-select signal fall delay time 1 (/cs3-0), (/cs3-1) t csdf1 fi g 9-3 to fi g 9-7 20 ns f19 chip-select signal rise delay time 1 (/cs3-0), (/cs3-1) t csdr1 20 ns f20 chip-select signal fall delay time 2 (/cs0) t csdf2 fi g 9-7 +10 ns f21 chip-select signal rise delay time 2 (/cs0) t csdr2 +10 ns f22 chip-select signal hold time 1 (/cs3-0) t csh1 fig 9-3 fi g 9-4 5 ns f23 chip-select signal hold time 2 (/cs3-0) t csh2 fig 9-5 fig 9-6 ns f24 address latch signal fall delay time (ale) t aledf -10 ns f25 address latch signal pulse width (ale) t alepw fi g 9-5 -10 ns f26 address latch signal hold time 1 (ale) t aleh1 fig 9-6 5 ns f27 address latch signal hold time 2 (ale) t aleh2 ns t c y c 4 t cyc 4 t c y c 4 t c y c 4 t c y c 2 t c y c 4
177 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max data transfer signal output timing 3 f28 read enable signal fall delay time 1 (/re) t redf1 fig 9-3 fig 9-4 10 ns f29 read enable signal fall delay time 2 (/re) t redf2 fig 9-5 fig 9-6 15 ns f30 read enable signal fall delay time 3 (/re) t redf3 fig 9-7 20 ns f31 read enable signal rise delay time 1 (/re) t redr1 fig 9-3 to fig 9-6 15 ns f32 read enable signal rise delay time 2 (/re) t redr2 +10 ns f33 read enable signal hold time (/re) t reh fi g 9-7 ns f34 burst rom read enable signal fall delay time (/bstre) t bredf 20 ns f35 burst rom read enable signal rise delay time (/bstre) t bredr +10 ns f36 write enable signal fall delay time 1 (/weh, wel) t wedf1 fig 9-3 fig 9-4 15 ns f37 write enable signal fall delay time 2 (/weh, wel) t wedf2 fig 9-5 fig 9-6 20 ns f38 write enable signal fall delay time 3 (/weh, wel) t wedf3 fig 9-7 ns f39 write enable pulse width time 1 (/weh, wel) t wepw1 fig 9-3 -20 ns f40 write enable pulse width time 2 (/weh, wel) t wepw2 fig 9-4 -10 ns f41 write enable pulse width time 3 (/weh, wel) t wepw3 fig 9-5 -10 ns f42 write enable pulse width time 4 (/weh, wel) t wepw4 fig 9-6 ns t c y c 4 t c y c 4 t c y c 4 t c y c 4 t c y c 2 t c y c 4 t c y c 3 4 ? tcyc -10
178 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 4.5 v to 5.5 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max serial interface signal output timing (synchronous serial transmission) transfer data delay time fig 9-10 normal ns f43 (sbo1-0) t txdd fig 9-11 fig 9-12 i 2 ct cyc ? 2ns f44 transfer data hold time (transfer in progress) (sbo1-0) t txdh1 fig 9-10 10 ns transfer data hold time f45 (transfer end timing at sbt input) t txdh2 fig 9-11 ns (sbo1-0) transfer data hold time f46 (transfer end timing at sbt output) t txdh3 fig 9-12 ns (sbo1-0) t c y c 2 t c y c 2 t sch + t scl 2
179 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-1-2 electrical characteristics 3 v structure cmos integrated circuit application general purpose function 16-bit m icrocontroller pin configuration figure 1-4-1 external dimensions figure 1-5-1 a. absolute maximum ratings v ss = 0 v parameter sy mbol ra ting unit a1 power supply voltage v dd - 0.3 to + 7.0 v a2 input pin voltage v i - 0.3 to v dd + 0.3 v a3 output pin voltage v o - 0.3 to v dd + 0.3 v a4 input/output pin voltage v io - 0.3 to v dd + 0.3 v a5 operating ambient temperature topr - 40 to + 85 c a6 storage temperature tstg -55 to + 125 c note: 1. absolute maximum ratings are stress ratings not to cause damage to the device. operation at these ratings is not guaranteed. 2. all of the v dd and vss pins are external pins. connect them directly to the power source and ground. 3. to prevent latch-up tolerance, connect more than one by-pass condenser between power supply pins and ground. use at least 0.2 f condenser.
180 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix b. operating conditions v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max b1 power supply voltage v dd 2.7 3 3.6 v crystal oscillator 1 (osci) b2 oscillator frequency f osc 1 410 mhz crystal oscillator 2 (xi) b3 oscillator frequency f osc 2 32 200 khz
181 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix c. electrical characteristics 1. dc characteristics v dd = 3.0 v v ss = 0 v ta = -40 c to +85 c capacitance parameter sy mbol conditions unit min typ max c1 power supply current during operation i dd 1 v i = v dd or v ss f osc 1 = 10 mhz output pins open 20 ma c2 power supply current during slow mode i dd 2 v i = v dd or v ss f osc 2 = 32 khz output pins open 5 ma c3 power supply current in stop mode i dd 3 oscillator stop all functions stop 50 a c4 power supply current in halt0 mode i dd 4 fosc1 = 10 mhz fosc2 = 32 khz 8 ma c5 power supply current in halt1 mode i dd 5 fosc1 = oscillator stop fosc2 = 32 khz 100 a
182 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max input/output pins 1 < output pushpull/input cmos level schmidt trigger > tmnio(n=0 to 5), tmnioa(n=6, 7), tmniob(n=6, 7), tmnic(n=6, 7), adsep c6 input high voltage v ih1 v dd ? 0.8 v v il1 only adsep pin v dd ? 0.1 v v il2 other pins v dd ? 0.2 v c8 output high voltage v oh1 i oh = -2.0 ma v dd -0.6 v c9 output low voltage v ol1 i ol = 2.0 ma 0.3 v c10 output leakage current i lo1 vo = hi-z +/- 10 a input/output pins 2 < output pushpull/input cmos level schmidt trigger/programmable pullup > sbo1, sbi1, sbt1, sbo0, sbi0, sbt0 c11 input high voltage v ih2 v dd ? 0.8 v c12 input low voltage v il3 v dd ? 0.2 v c13 output high voltage v oh2 i oh = -2.0 ma v dd -0.6 v c14 output low voltage v ol2 i ol = 2.0 ma 0.3 v c15 output leakage current i lo2 vo = hi-z +/- 10 a c16 pullup resistance p pu1 v i = v ss 20 60 180 k ? input low voltage c7
183 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max input/output pins 3 < output pushpull/input ttl level schmidt trigger/programmable pullup > wait, /re, /wel. /weh, /cs3 to /cs0, ale, a19 to a0, /irq4 to /irq0 c17 input high voltage v ih3 2.1 v c18 input low voltage v il4 0.4 v c19 output high voltage v oh3 i oh = -2.0 ma v dd -0.6 v c20 output low voltage v ol3 i ol = 2.0 ma 0.3 v c21 output leakage current i lo3 vo = hi-z +/- 10 a c22 pullup resistance p pu2 v i = v ss 20 60 180 k ? input/output pins 4 < output pushpull/input ttl level schmidt trigger > /breq, /brack, /word c23 input high voltage v ih4 2.1 v c24 input low voltage v il5 0.4 v c25 output high voltage v oh4 i oh = -2.0 ma v dd -0.6 v c26 output low voltage v ol4 i ol = 2.0 ma 0.3 v c27 output leakage current i lo4 vo = hi-z +/- 10 a
184 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max input/output pins 5 < output pushpull/input ttl level schmidt trigger/programmable pullup > d15 to d0 c28 input high voltage v ih5 2.1 v c29 input low voltage v il6 0.4 v c30 output high voltage v oh5 i oh = -2.0 ma v dd -0.6 v c31 output low voltage v ol5 i ol = 2.0 ma 0.3 v c32 output leakage current i lo5 vo = hi-z +/- 10 a c33 pullup resistance p pu3 v i = v ss 20 60 180 k ? input/output pins 6 < output pushpull/analog input > an3 to an0 c34 input high voltage v ih6 v dd ? 0.8 v c35 input low voltage v il7 v dd ? 0.2 v c36 output high voltage v oh6 i oh = -2.0 ma v dd -0.6 v c37 output low voltage v ol6 i ol = 2.0 ma 0.3 v c38 output leakage current i lo6 vo = hi-z +/- 10 a
185 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol co nditions unit min typ max input/output pins 7 < output pushpull/analog input/programmable pullup > a23 to a20 c39 input high voltage v ih7 v dd ? 0.8 v c40 input low voltage v il8 v dd ? 0.2 v c41 output high voltage v oh7 i oh = -2.0 ma v dd -0.6 v c42 output low voltage v ol7 i ol = 2.0 ma 0.3 v c43 output leakage current i lo7 vo = hi-z +/- 10 a c44 pullup resistance p pu4 v i = v ss 20 60 180 k ? input/output pins 8 < input cmos level schmidt trigger/output open-drain/pullup > /rst c45 input high voltage v ih8 v dd ? 0.9 v c46 input low voltage v il9 v dd ? 0.1 v c47 pullup resistance p pu5 v i = v ss 20 60 180 k ?
186 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol c onditions unit min typ max output pin < output pushpull > sysclk c48 output high voltage v oh8 i oh = -2.0 ma v dd -0.6 v c49 output low voltage v ol8 i ol = 2.0 ma 0.3 v c50 output leakage current i lo8 vo = hi-z +/- 10 v input pins < input cmos level schmidt trigger > /nmi, mode c51 input high voltage v ih9 v dd ? 0.9 v c52 input low voltage v il10 v dd ? 0.1 v c53 input leakage current v lo9 v dd = 3.3 v v i = v ss to v dd +/- 10 a osci pin, xi pin (at external clock input) : crystal, ceramic self-excited oscillation see figure 1-4-2 to figure 1-4-3 c54 input high voltage v ih10 v dd ? 0.8 v dd v c55 input low voltage v il11 v ss v dd ? 0.2 v pin capacitance c56 input pin c in 715 pf c57 output pin c out v in = 0 v ta=25 c 715 pf c58 input/output pin c i/o 715 pf
187 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix d. a/d converter characteristics v dd = 3.0 v v ss = 0 v ta = 25 c capacitance parameter sy mbol conditions unit min typ max d1 resolution 8 bits +/- 3 lsb +/- 4 lsb d3 a/d conversion time fosc = 10 mhz 9.6 s d4 a/d conversion cycle fosc = 10 mhz 9.6 s d5 analog input voltage v ia v ss v dd v a/d conversion relative p recision v dd = 3.0 v v ss = 0 v an3-0 an7-4 d2
188 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix e. ac characteristics v dd = 2.7 v to 3.6 v in p ut timin g conditions v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max external clock input timing (fosc1 = 10 mhz) e1 external clock input cycle time t exccyc 100 ns e2 external clock input high pulse width t exch -5 ns e3 external clock input low pulse width t excl fig 9-1 -5 ns e4 external clock input rise time t excr 5 ns e5 external clock input fall time t excf 5 ns reset input timing e6 reset signal pulse width (/rst) t rstw fig 9-2 4 t exccyc t exccyc 2 t exccyc 2
189 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v in p ut timin g conditions v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol conditions unit min typ max data transfer signal input timing e7 data acknowledge signal setup time (wait) t waits fi g 9-4 20 ns e8 data acknowledge signal hold time (wait) t waith fig 9-6 0 ns data transfer signal input timing e9 read data setup time (d15-00) t rds fig 9-3 fi g 9-4 40 ns e10 read data hold time (d15-00) t rdh fig 9-5 fig 9-6 0 ns bus authority request input timing e11 bus authority request signal setup time (/breq) t breqs fi g 9-8 0 ns e12 bus authority request signal hold time (/breq) t breqh 0 ns interrupt signal input timing e13 nonmaskable interrupt signal pulse width (nmi) t nmiw fi g 9-9 5 (note) t cyc e14 external interrupt signal pulse width (/irq4-0) t irqw 2 (note) t cyc note : an interru p t ma y occur when the noise of the s p ecified time or less is in p ut.
190 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v in p ut timin g conditions v ss = 0 v ta = -40 c to +85 c capacitance parameter symbol c onditions unit min typ max serial interface related signal timing (synchronous serial reception) e15 data reception setup time (sbi1-0) t rxds 25 ns e16 data reception hold time (sbi1-0) t rxdh fi g 9-13 25 ns e17 serial clock input high pulse width (sbt1-0) t sch t cyc+100 ns e18 serial clock input low pulse width (sbt1-0) t scl t cyc+100 ns timer/counter signal input timing e19 timer external input clock low pulse width (tmnio: n=5-0) (tmnioa, tmniob, tmnic: n=6,7) t tcclkl fi g 9-14 t cyc ns e20 timer external input clock high pulse width (tmnio: n=5-0) (tmnioa, tmniob, tmnic: n=6,7) t tcclkh t cyc ns
191 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix f. ac characteristics (output) v dd = 2.7 v to 3.6 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max system clock output timing f1 system clock output cycle time (sysclk) t cyc 200 ns f2 system clock output low pulse width (sysclk) t cl 90 ns f3 system clock output high pulse width (sysclk) t ch fig 9-1 90 ns f4 system clock output rise time (sysclk) t cr 20 ns f5 system clock output fall time (sysclk) t cf 20 ns
192 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max data transfer signal output timing 1 f6 address delay time 1 (a23-0), (a23-16) t ad1 fig 9-3 to fig 9-6 50 ns f7 address delay time 2 (ad15-0) t ad2 fig 9-5 fig 9-6 +40 ns f8 address hold time 1 (a23-0), (a23-16) t ah1 fig 9-3 fig 9-4 5 ns f9 address hold time 2 (a23-0), (a23-16) t ah2 fig 9-5 fig 9-6 ns f10 address hold time 3 (ad15-0) t ah3 -30 ns f11 address/data hold time 1 (ad15-0) t adh1 fig 9-5 fig 9-6 5 ns f12 address/data hold time 2 (ad15-0) t adh2 ns f13 data delay time 1 (d15-0) t dd1 fig 9-3 fig 9-4 40 ns f14 data delay time 2 (ad15-0) t dd2 fig 9-5 fig 9-6 ns f15 data delay time 3 (d15-0) t dd3 fig 9-7 ns f16 data hold time 1 (d15-0) t dh1 fi g 9-3 5 ns f17 data hold time 2 (d15-0) t dh2 fig 9-4 ns t c y 4 t cy 4 t cyc 4 t cy 4 t cy 4 t cy 2 t c y 4 t cy 4
193 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max data transfer signal output timing 2 f18 chip-select signal fall delay time 1 (/cs3-0), (/cs3-1) t csdf1 fi g 9-3 to fi g 9-7 40 ns f19 chip-select signal rise delay time 1 (/cs3-0), (/cs3-1) t csdr1 40 ns f20 chip-select signal fall delay time 2 (/cs0) t csdf2 fi g 9-7 +30 ns f21 chip-select signal rise delay time 2 (/cs0) t csdr2 +30 ns f22 chip-select signal hold time 1 (/cs3-0) t csh1 fig 9-3 fi g 9-4 5 ns f23 chip-select signal hold time 2 (/cs3-0) t csh2 fig 9-5 fig 9-6 ns f24 address latch signal fall delay time (ale) t aledf -10 ns f25 address latch signal pulse width (ale) t alepw fi g 9-5 -30 ns f26 address latch signal hold time 1 (ale) t aleh1 fig 9-6 5 ns f27 address latch signal hold time 2 (ale) t aleh2 ns t c y c 4 t c y 4 t cyc 4 t cyc 4 t cyc 2 t cyc 4
194 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max data transfer signal output timing 3 f28 read enable signal fall delay time 1 (/re) t redf1 fig 9-3 fig 9-4 20 ns f29 read enable signal fall delay time 2 (/re) t redf2 fig 9-5 fig 9-6 30 ns f30 read enable signal fall delay time 3 (/re) t redf3 fig 9-7 40 ns f31 read enable signal rise delay time 1 (/re) t redr1 fig 9-3 to fig 9-6 30 ns f32 read enable signal rise delay time 2 (/re) t redr2 +20 ns f33 read enable signal hold time (/re) t reh fi g 9-7 ns f34 burst rom read enable signal fall delay time (/bstre) t bredf 40 ns f35 burst rom read enable signal rise delay time (/bstre) t bredr +20 ns f36 write enable signal fall delay time 1 (/weh, wel) t wedf1 fig 9-3 fig 9-4 30 ns f37 write enable signal fall delay time 2 (/weh, wel) t wedf2 fig 9-5 fig 9-6 40 ns f38 write enable signal fall delay time 3 (/weh, wel) t wedf3 fig 9-7 ns f39 write enable pulse width time 1 (/weh, wel) t wepw1 fig 9-3 -20 ns f40 write enable pulse width time 2 (/weh, wel) t wepw2 fig 9-4 -10 ns f41 write enable pulse width time 3 (/weh, wel) t wepw3 fig 9-5 -10 ns f42 write enable pulse width time 4 (/weh, wel) t wepw4 fig 9-6 ns t cy 4 t c y 4 t cy 4 t cy 4 t cyc 2 t cy 4 t c y c 3 4 ? tcyc -10
195 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix v dd = 2.7 v to 3.6 v out p ut si g nal characteristics v ss = 0 v ta = -40 c to +85 c c l = 70 p f capacitance parameter symbol conditions unit min typ max serial interface signal output timing (synchronous serial transmission) transfer data delay time fig 9-10 normal ns f43 (sbo1-0) t txdd fig 9-11 fig 9-12 i 2 ct cyc ? 2 ns f44 transfer data hold time (transfer in progress) (sbo1-0) t txdh1 fig 9-10 10 ns transfer data hold time f45 (transfer end timing at sbt input) t txdh2 fig 9-11 ns (sbo1-0) transfer data hold time f46 (transfer end timing at sbt output) t txdh3 fig 9-12 ns (sbo1-0) t cyc 2 t cy 2 t sch + t scl 2
196 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix cycle time pulse width high fall time rise time ac timing voltage level pulse width low v dd 0.9 delay time cycle time pulse width high fall time rise time pulse width low input signal output signal output signal (both setup time and hold time are v dd 0.5) v dd 0.1 v dd 0.9 v dd 0.1 v dd 0.1 v dd 0.9 v dd 0.1 v dd 0.1 v dd 0.1 v dd 0.9 v dd 0.9 v dd 0.9 v dd 0.5 v dd 0.5
197 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix fig. 9-1 system clock timing f osc 1 t exccyc t exch t excl t excf t excr sysclk t cyc t ch t cl t cf t cr fig. 9-2 reset timing rst t rstw
198 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix sysclk /cs3-0 t ch /re a23-00 d15-00 t cyc t cl t ad1 t csdf1 t csdr1 t csh2 t csh1 t ah1 t ah2 t t t data t rds t rdh t redf1 t redr1 d15-00 /wel,/weh (normal) wedf 1 t wepw 1 wepw 2 data t dh1 dh2 t dd1 /wel,/weh (we short mode) t ad1 fig. 9-3 data transfer signal timing (address/data separated mode, without wait) t repw 1 (normal)
199 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix sysclk t cyc fig. 9-4 data transfer signal timing (address/data separated mode, with wait) d15-00 cs3-0 t cl t ch wel,weh (normal) t ch re a23-00 d15-00 wait t cyc (n-1)* t cyc data data wel,weh (we short mode) t cl t ad1 t csdf1 t redf1 t dd1 t wedf 1 t wepw 1 t dh1 t dh2 t redr1 t rds t rdh t csdr1 t csh2 t csh1 t ah1 t ah2 t wepw 2 t waits t waith t waits t waith t waits t waith t ad1 *: n is the number of waits (n 1)
200 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix sysclk t cyc fig. 9-5 data transfer signal timing (address/data shared mode, without wait) ad15-08 cs3-0 t cl t ch wel,weh (normal) t ch re a23-16 t cyc ad07-00 (16-bit bus mode) data wel,weh (we short mode) t cl ale * note 1 address ad15-08 ad07-00 (16-bit bus mode) address data ad07-00 (8-bit bus mode) address t ad1 t ad1 t ah1 t csdf1 t csdr1 t csh2 t csh1 t ah2 t ad2 t alepw t aledf t ah3 t ad2 t ad2 t dd2 t redf 2 t redr 1 t adh2 t adh1 t rds t rdh t adh1 t adh2 t wedf 2 aleh2 t wepw 4 t wepw 3 t ah3 t aleh1
201 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix sysclk t cyc ad15-08 cs3-0 t cl t ch wel,weh (normal) t ch re a23-16 wait t cyc ad07-00 (16-bit bus mode) data wel,weh (we short mode) t cl ale * note 1 address ad15-08 ad07-00 (16-bit bus mode) address data ad07-00 (8-bit bus mode) address t ad1 t ad1 t ah1 t csdf1 t csdr1 t csh2 t csh1 t ah2 t waits t waith t waits t waith t ad2 t alepw t aledf t ah3 t ad2 t ad2 t dd2 t redf 2 t redr 1 t adh2 t adh1 t rds t rdh t adh1 t adh2 t wedf 2 t aleh2 t wepw 4 t wepw 3 t ah3 t aleh1 t cyc (n-1)* *: n is the number of waits (n 1) fig. 9-6 data transfer signal timing (address/data shared mode, with wait)
202 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix sysclk t cyc fig. 9-7 data transfer signal timing (burst rom interface) cs0 t cl t ch a23-00 t cyc n t cyc t ch t cl t ch t cl t ch t cl t ch t cl t ch t cl t cyc t cyc t cyc (penarty-cyc.) (rom-read) (rom-read) (rom-read) (notrom-read) re cs3-1 cs0 a23-00 (rom-read) (rom-read) (rom-read) (notrom-access) bstre cs3-1 (rom-read) re t csdf2 t csdr2 t csdf1 t csdr1 t redr 2 t redf 3 t redf 1 t redr 1 t csdf2 t csdr2 t csdf1 t csdr1 (read) wel,weh (write) d15-00 t bredf t bredr t reh t dd3 t wedf 3
203 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix fig. 9-9 interrupt signal timing irq3-0 t irqw fig. 9-10 serial interface signal timing 1 (synchronous serial transmission: transfer in progress) sbt1-0 t txdd sbo1-0 nmi t nmiw fig. 9-8 bus authority request signal timing breq brack t breqs t breqh t txdh 1 fig. 9-11 serial interface signal timing 2 (synchronous serial transmission: transfer end timing at sbt input) sbt1-0 sbo1-0 t txdd t txdh 2
204 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix tmnio(n=5-0) fig. 9-14 timer/counter signal timing t tcclkl t tcclkh tmnioa(n=6,7) tmniob(n=6,7) tmnic(n=6,7) t rxds t rxdh fig. 9-13 serial interface signal timing 4 (synchronous serial reception) sbt1-0 sbi1-0 t scl t sch fig. 9-12 serial interface signal timing 3 (synchronous serial transmission: transfer end timing at sbt output) sbt1-0 sbo1-0 t txdd t txdh 3
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 205 a b c d e f g h i j k l m n o p q r s t u v w x y z 9-2 data appendix 9-2-1 list of special registers
chapter 9 appendix 206 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g flag description bit number chapter 9 appendix mn102h55d/55g/f55g 9-69 a b c d e f g h i j k l m n o p q r s t u v w x y z 1514131211109876543210 at3 at3 at3 at3 at3 at3 at3 at3 - - - - at3 at3 at3 at3 en md1 md0 bw db8 di sb8 si iq3 iq2 iq1 iq0 r/wr/wr/wr/wr/wr/wr/wr/wrrrrr/wr/wr/wr/w 0000000000000000 0/10/10/10/10/10/10/10/100000/10/10/10/1 at3ctr : x'00fd30' atc 3 control register 16-bit access register 0: disable 1: transfer start/transfer in progress 00: one byte/word transfer 01: burst transfer 10: two bytes/words transfer 11: reserved 0: byte 1: word 0: 16-bit 1: 8-bit 0: fixed 1: increment 0: 16-bit 1: 8-bit 0: fixed 1: increment 0000: software initialization 0001: /dmareq1 pin input 0010: external interrupt 2 0011: external interrupt 3 0100: timer 2 underflow interrupt 0101: timer 6 underflow interrupt 0110: timer 8 capture b interrupt 0111: timer 10 underflow interrupt 1000: timer 11 capture a interrupt 1001: timer 12 capture b interrupt 1010: serial 2 transmission end interrupt 1011: serial 2 reception end interrupt 1100: serial 3 transmission end interrupt 1101: serial 3 reception end interrupt 1110: a/d conversion end interrupt 1111: key interrupt 15 transfer busy/start flag 14,13 transfer mode 12 transfer units 11 destination bus width 10 destination pointer increment 9 source bus width 8 source pointer increment 3-0 atc activation factor setup sets the atc3 operating control conditions. selecting the two bytes/words transfer mode is valid only in byte access. the lsb of the address in the first word forcibly becomes 0, and the lsb of the address in the second word forcibly becomes 1. selecting word as the unit is not allowed when 8-bit bus width is allowed in the external memory space. selecting 8-bit desitination bus width or 8-bit source bus width is allowed only when 8-bit bus width is selected in the external memory space. when destination pointer incre- ment or source pointer incre- ment is selected, the pointer in- crements by 1 in byte access and by 2 in word access. the at3iq0 ~ 3 bits are cleared to 0 by the atc3 transfer end interrupt. value at reset about this section description of each page each page of this chapter describes one or more registers. each page lists the register name, address, register access, bit map, flag explanation of each bit number and supplementary explanation. the following is the layout and definition of this section. access bit map bit number flag name r: read only w: write only r/w: read/write read value 0: always 0 1: always 1 register access register name address supplemental explanation
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 207 a b c d e f g h i j k l m n o p q r s t u v w x y z cpum : x'00fc00' cpu mode control register 16-bit access register 1514131211109876543210 wdwdwd--------osc stop halt osc1 osc0 rst lng1 lng0 id r/wr/wr/wrrrrrrrrrr/wr/wr/wr/w 1000011100110111 0/10/10/1000000000/10/10/10/10/1 setting wdrst to '0' after set- ting it to '1' clears the watchdog timer counting value and starts counting. the watchdog timer consists of a 17-bit binary counter counting on the oscilla- tion clock. therefore, clear the watchdog timer counting value within 2 16 (65,536) machine cycles. 15 watchdog timer enable 14:13 watchdog timer count * 4 system clock monitor 3 cpu operating control (stop tranfer request) 2 cpu operating control (halt tranfer request) 1:0 oscillator control 0: enable 1: disable and clear 00: 2 16 01: 2 4 10: 2 8 11: reserved 0: high-speed 1: low-speed 0000: normal mode 0001: idle mode 0011: slow mode 0100: halt0 mode 0111: halt1 mode 1000: stop0 mode 1011: stop1 mode the following describes programming rules and precautions in the stop/halt mode. points for programming (1) setting the cpum address in the address register in advance, set the cpum register using the mov instruction with the register indirect addressing mode. (2) immediately after the mov instruction, locate three nops consecutively. (3) immediately before the mov instruction, locate the jmp instruction and align to the even address. this avoids the effects by the differences of the bus widths in the memory mode or expansion mode and provides the same result when operating in any conditions. programming coding example in assembler (as 102ver.1.0, ver.2.0) mov cpum, a0 ; set a0 to the cpum address. mov (a0), d0 ; transfer the contents of cpum to d0. or x'000*', d0 ; generate the data to set the stop/halt mode. jmp stp_hlt ; branch unconditionally to the even address to align 2 ; eliminate the difference of operating conditions. stp_hlt mov d0, (a0) ; set the stop/halt mode to cpum. nop ; dummy nop ; dummy nop ; dummy precautions (1) * of or instruction varies depending on the stop or halt mode. (2) set the align value to '2' or more in the above file when the align value is set using section dummy instruction before this programming coding is described. (3) code the above programming in another file of the assembler source file when the program is developed with c complier cc 102. changing the set value reduces the wait time for oscillation sta- bilization when returning from stop mode. (at reset release, the wait time for oscillation stabliation is 2 16 (65,536) ma- chine cycles.
chapter 9 appendix 208 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g memctr : x'00fc02' memory control register 16-bit access register 1514131211109876543210 ----- hswt nwait wait arb - wait wait - wait wait wait ioe ioe set sz io1 io0 2 1 0 rrrrrr/wr/wr/wr/wrr/wr/wrr/wr/wr/w 0000011100110111 000000/10/10/10/1000/100/10/10/1 10 peripheral fixed wait cycle enable flag during handshake mode 9 peripheral fixed wait cycle enable flag 8 fixed wait mode/ handhsake mode switch 7 bus width setup flag for fixed area (x'040000' to x'07ffff') 5:4 peripheral fixed wait cycle 2:0 fixed wait cycle 0: no wait 1: peripheral fixed wait cycle (always set '1' in this series.) 0: enable 1: disable (always set '0' in this series.) 0: handshake mode 1: fixed wait mode (always set '0' in this series.) 0: based on /word pin 1: 8-bit bus access regardless of /word pin 00: no wait 01: 1 wait cycle 10: 2 wait cycles 11: 3 wait cycles (always set '01' in this series.) 000: no wait cycle 001: 1 wait cycle 010: 2 wait cycles 011: 3 wait cycles 100: 4 wait cycles 101: 5 wait cycles 110: 6 wait cycles 111: 7 wait cycles (don't care in this series.) in this series, set memctr to x'0410' or x'0490'.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 209 a b c d e f g h i j k l m n o p q r s t u v w x y z ----------gn4gn3gn2gn1gn0- rrrrrrrrrrrrrrrr 0000000000000000 00000000000/10/10/10/10/10 1514131211109876543210 iagr : x'00fc0e' interrupt accept group register 8/16-bit access register 5:1 group number of accepted interrupt iagr is a read-only register. -------------- wait wait 10 rrrrrrrrrrrrrrr/wr/w 0000000000000000 000000000000000/10/1 1514131211109876543210 memmd0 : x'00fc30' memory mode control register 0 16-bit access register set any values when block 0 is unused. 1:0 wait cycle for block 0 00: no wait 01: 1 wait cycle 10: 2 wait cycles 11: handshake
chapter 9 appendix 210 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g ------- bmod - - ---- wait wait 10 rrrrrrrr/wrrrrrrr/wr/w 0000000000000000 00000000/10000000/10/1 1514131211109876543210 memmd1 : x'00fc32' memory mode control register 1 16-bit access register set any values when block 1 is unused. 8 bus mode for block 1 1:0 wait cycle for block 1 0: 16-bit bus mode 1: 8-bit bus mode 00: no wait 01: 1 wait cycle 10: 2 wait cycles 11: handshake ------- bmod - - ---- wait wait 10 rrrrrrrr/wrrrrrrr/wr/w 0000000000000000 00000000/10000000/10/1 1514131211109876543210 memmd2 : x'00fc34' memory mode control register 2 16-bit access register set any values when block 2 is unused. 8 bus mode for block 2 1:0 wait cycle for block 2 0: 16-bit bus mode 1: 8-bit bus mode (select the same bus width as the bus width set by /word pin.) 00: no wait 01: 1 wait cycle 10: 2 wait cycles 11: handshake
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 211 a b c d e f g h i j k l m n o p q r s t u v w x y z ------------- unif wdif nmif rrrrrrrrrrrrrr/wr/wr/w 0000000000000000 00000000000000/10/10/1 1514131211109876543210 g0icr : x'00fc40' nonmaskable interrupt control register 0 8/16-bit access register 2 nonmaskable interrupt request flag by executing undefined instruction 1 nonmaskable interrupt request flag by overflowing watchdog timer 0 nonmaskable interrupt request flag by /nmi pin 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested ------- bmod - - - - - - wait wait 10 rrrrrrrr/wrrrrrrr/wr/w 0000000000000000 00000000/10000000/10/1 1514131211109876543210 memmd3 : x'00fc36' memory mode control register 3 16-bit access register set any values when block 3 is unused. 8 bus mode for block 3 1:0 wait cycle for block 3 0: 16-bit bus mode 1: 8-bit bus mode 00: no wait 01: 1 wait cycle 10: 2 wait cycles 11: handshake
chapter 9 appendix 212 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g - g1 g1 g1 - tm5 tm0 irq0 - tm5 tm0 irq0 - tm5 tm0 irq0 lv2 lv1 lv0 ie ie ie ir ir ir id id id r r/w r/w r/w r r/w r/w r/w r r/w r/w r/w r r/w r/w r / w 0000000000000000 0 0/1 0/1 0/1 0 0/1 0/1 0/1 0 0/1 0/1 0/1 0 0/1 0/1 0/1 1514131211109876543210 g1icr : x'00fc42' maskable interrupt control register 1 8/16-bit access register 14:12 group 1 interrupt priority level 10 timer 5 underflow interrupt enable flag 9 timer 0 underflow interrupt enable flag 8 irq0 interrupt enable flag 6 timer 5 underflow interrupt request flag 5 timer 0 underflow interrupt request flag 4 irq0 interrupt request flag 2 timer 5 underflow interrupt detect flag 1 timer 0 underflow interrupt detect flag 0 irq0 interrupt detect flag 000 (level 0) to 110 (level 6) 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected set '1' when timer 5 underflows. set '1' when timer 0 underflows. set '1' when an external inter- rupt occurs from irq0 pin.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 213 a b c d e f g h i j k l m n o p q r s t u v w x y z - g2 g2 g2 - an tm1 irq1 - an tm1 irq1 - an tm1 irq1 lv2 lv1 lv0 ie ie ie ir ir ir id id id r r/w r/w r/w r r/w r/w r/w r r/w r/w r/w r r/w r/w r / w 0000000000000000 0 0/1 0/1 0/1 0 0/1 0/1 0/1 0 0/1 0/1 0/1 0 0/1 0/1 0/1 1514131211109876543210 g2icr : x'00fc44' maskable interrupt control register 2 8/16-bit access register 14:12 group 2 interrupt priority level 10 a/d conversion end interrupt enable flag 9 timer 1 underflow interrupt enable flag 8 irq1 interrupt enable flag 6 a/d conversion end interrupt request flag 5 timer 1 underflow interrupt request flag 4 irq1 interrupt request flag 2 a/d conversion end interrupt detect flag 1 timer 1 underflow interrupt detect flag 0 irq1 interrupt detect flag 000 (level 0) to 110 (level 6) 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected set '1' when the a/d conversion ends. set '1' when timer 1 underflows. set '1' when an external inter- rupt occurs from irq1 pin.
chapter 9 appendix 214 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g - g3 g3 g3 sc0r sc0t tm2 irq2 sc0r sc0t tm2 irq2 sc0r sc0t tm2 irq2 lv2 lv1 lv0 ie ie ie ie ir ir ir ir id id id id r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r / w 0000000000000000 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 14:12 group 3 interrupt priority level 11 serial 0 reception end interrupt enable flag 10 serial 0 transmission end interrupt enable flag 9 timer 2 underflow interrupt enable flag 8 irq2 interrupt enable flag 7 serial 0 reception end interrupt request flag 6 serial 0 transmission end interrupt request flag 5 timer 2 underflow interrupt request flag 4 irq2 interrupt request flag 3 serial 0 reception end interrupt detect flag 2 serial 0 transmission end interrupt detect flag 1 timer 2 underflow interrupt detect flag 0 irq2 interrupt detect flag 000 (level 0) to 110 (level 6) 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected g3icr : x'00fc46' maskable interrupt control register 3 8/16-bit access register set '1' when the serial 0 recep- tion ends. set '1' when the serial 0 trans- mission ends. set '1' when timer 2 underflows. set '1' when an external inter- rupt occurs from irq2 pin.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 215 a b c d e f g h i j k l m n o p q r s t u v w x y z - g4 g4 g4 sc1r sc1t tm3 irq3 sc1r sc1t tm3 irq3 sc1r sc1t tm3 irq3 lv2 lv1 lv0 ie ie ie ie ir ir ir ir id id id id r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r / w 0000000000000000 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 14:12 group 4 interrupt priority level 11 serial 1 reception end interrupt enable flag 10 serial 1 transmission end interrupt enable flag 9 timer 3 underflow interrupt enable flag 8 irq3 interrupt enable flag 7 serial 1 reception end interrupt request flag 6 serial 1 transmission end interrupt request flag 5 timer 3 underflow interrupt request flag 4 irq3 interrupt request flag 3 serial 1 reception end interrupt detect flag 2 serial 1 transmission end interrupt detect flag 1 timer 3 underflow interrupt detect flag 0 irq3 interrupt detect flag 000 (level 0) to 110 (level 6) 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected g4icr : x'00fc48' maskable interrupt control register 4 8/16-bit access register set '1' when the serial 1 recep- tion ends. set '1' when the serial 1 trans- mission ends. set '1' when timer 3 underflows. set '1' when an external inter- rupt occurs from irq3 pin.
chapter 9 appendix 216 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g - g5 g5 g5 *note *note tm4 irq4 *note *note tm4 irq4 - - tm4 irq4 lv2 lv1 lv0 ie ie ir ir id id rr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wrrrr 0000000000000000 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 0/1 0/1 1514131211109876543210 g5icr : x'00fc4a' maskable interrupt control register 5 8/16-bit access register 14:12 group 5 interrupt priority level 9 timer 4 underflow interrupt enable flag 8 irq4 interrupt enable flag 5 timer 4 underflow interrupt request flag 4 irq4 interrupt request flag 1 timer 4 underflow interrupt detect flag 0 irq4 interrupt detect flag 000 (level 0) to 110 (level 6) 0: disable 1: enable 0: disable 1: enable 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected set '1' when timer 4 underflows. set '1' when an external inter- rupt occurs from irq4 pin. *note: always set 0.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 217 a b c d e f g h i j k l m n o p q r s t u v w x y z - g6 g6 g6 atc tm6b tm6a tm6u atc tm6b tm6a tm6u atc tm6b tm6a tm6u lv2 lv1 lv0 ie ie ie ie ir ir ir ir id id id id r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r 0000000000000000 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 g6icr : x'00fc4c' maskable interrupt control register 6 8/16-bit access register 14:12 group 6 interrupt priority level 11 atc transfer end interrupt enable flag 10 timer 6 compare/capture interrupt b enable flag 9 timer 6 compare/capture interrupt a enable flag 8 timer 6 underflow interrupt enable flag 7 atc transfer end interrupt request flag 6 timer 6 compare/capture interrupt b request flag 5 timer 6 compare/capture interrupt a request flag 4 timer 6 underflow interrupt request flag 3 atc transfer end interrupt detect flag 2 timer 6 compare/capture interrupt b detect flag 1 timer 6 compare/capture interrupt a detect flag 0 timer 6 underflow interrupt detect flag 000 (level 0) to 110 (level 6) 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected set '1' when atc transfer ends. set '1' when a timer 6 underflow interrupt or compare/capture in- terrupt occurs.
chapter 9 appendix 218 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g - g7 g7 g7 - tm7b tm7a tm7u - tm7b tm7a tm7u - tm7b tm7a tm7u lv2 lv1 lv0 ie ie ie ir ir ir id id id rr/wr/wr/wrr/wr/wr/wrr/wr/wr/wrrrr 0000000000000000 0 0/1 0/1 0/1 0 0/1 0/1 0/1 0 0/1 0/1 0/1 0 0/1 0/1 0/1 1514131211109876543210 g7icr : x'00fc4e' maskable interrupt control register 7 8/16-bit access register 14:12 group 7 interrupt priority level 10 timer 7 compare/capture interrupt b enable flag 9 timer 7 compare/capture interrupt a enable flag 8 timer 7 underflow interrupt enable flag 6 timer 7 compare/capture interrupt b request flag 5 timer 7 compare/capture interrupt a request flag 4 timer 7 underflow interrupt request flag 2 timer 7 compare/capture interrupt b detect flag 1 timer 7 compare/capture interrupt a detect flag 0 timer 7 underflow interrupt detect flag 000 (level 0) to 110 (level 6) 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt requested 1: interrupt requested 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected 0: no interrupt detected 1: interrupt detected set '1' when a timer 7 underflow interrupt or compare/capture in- terrupt occurs.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 219 a b c d e f g h i j k l m n o p q r s t u v w x y z ------irq4irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 tg1 tg0 tg1 tg0 tg1 tg0 tg1 tg0 tg1 tg0 rrrrrrr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w 0000000000000000 0000000/10/10/10/10/10/10/10/10/10/1 1514131211109876543210 extmd : x'00fc50' external interrupt edge setup register irqtrg sets the trigger condi- tions for external interrupts. 8/16-bit access register 9:8 set trigger conditions for irq4 pin interrupt 7:6 set trigger conditions for irq3 pin interrupt 5:4 set trigger conditions for irq2 pin interrupt 3:2 set trigger conditions for irq1 pin interrupt 1:0 set trigger conditions for irq0 pin interrupt 00: low level 01: high level 10: negative edge 11: positive edge 00: low level 01: high level 10: negative edge 11: positive edge 00: low level 01: high level 10: negative edge 11: positive edge 00: low level 01: high level 10: negative edge 11: positive edge 00: low level 01: high level 10: negative edge 11: positive edge
chapter 9 appendix 220 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g we------ nale - - brpg brpg - - bren bren sht en 1 0 1 0 r/wrrrrrrr/wrrr/wr/wrrr/wr/w 0000000000000000 0/10000000/1000/10/1000/10/1 1514131211109876543210 exmctr : x'00fd00' external memory control register 8/16-bit access register 15 weh, wel pulse width shortening 8 ale signal polarity 5:4 page size of rom burst mode 1:0 rom burst mode 0: disbale 1: enable 0: positive logic 1: negative logic 00: 4 bytes 01: 8 bytes 10: 16 bytes 11: reserved 00: disable 01: reserved 10: enable (without penalty) 11: enable (with penalty) setting a page size of rom burst mode is invalid when rom burst mode is disabled. atc ovr - atc - - atc atc atc atc atc atc atc atc atc atc en ef dir end9 end8 end7 end6 end5 end4 end3 end2 end1 end0 r/w r/w r r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r / w 0000000000000000 0/1 0/1 0 0/1 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 atcctr : x'00fd10' atc control register 8/16-bit access register 15 atc enable 14 overrun error flag 13 atc transfer direction 9:0 atc end address 0: disbale 1: enable 0: no error 1: error 0: from serial ch 0 to internal ram 1: from internal ram to serial ch 0 set the atc end address (the lower 10 bits of the internal ram area) the upper 14 bits are fixed at '00000000111000' because the internal ram addresses for tc operation are x'00e000' to x'00e3ff'. set the larger value than the atcbc value.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 221 a b c d e f g h i j k l m n o p q r s t u v w x y z ------atcatcatcatcatcatcatcatcatcatc bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w 0000000000000000 0000000/10/10/10/10/10/10/10/10/10/1 1514131211109876543210 atcbc : x'00fd12' atc binary counter 8/16-bit access register 9:0 atc transfer address set the atc start address (the lower 10 bits of the internal ram area) (read the internal ram address where the chip accesses next during atc operation.)
chapter 9 appendix 222 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g sc0ctr : x'00fd80' serial 0 control register 15 transmit enable 14 receive enable 13 break transmission 12 i 2 c start or stop sequence 11 protocol selection 9 bit order selection 8i 2 c mode selection 7 character length 6:4 parity bit selection 3 stop bit selection 2 open-drain control for i 2 c pin 1:0 serial 0 clock source selection 0: disable 1: enable 0: disable 1: enable 0: don't break 1: break (set sbo to 0) 0: stop sequence output when changing this bit from 1 to 0. 1: start sequence output when changing this bit from 0 to 1. 0: asynchronous mode 1: clock synchronous mode, i 2 c mode 0: lsb first 1: msb first (select only when the character length is 8-bit.) 0: i 2 c mode off 1: i 2 c mode on 0: 7-bit 1: 8-bit 000: none 100: 0 (output low) 101: 1 (output high) 110: even (1s are even) 111: odd (1s are odd) others: reserved 0: 1-bit 1: 2-bit 0: off 1: on 00: sbt0 pin 01: timer 2 underflow/16 10: timer 2 underflow/2 11: timer 3 underflow/16 sc0 sc0 sc0 sc0 sc0 - sc0 sc0 sc0 sc0 sc0 sc0 sc0 sc0 sc0 sc0 ten ren bre i2c ptl od i2cm ln pty2 pty1 pty0 sb pod s1 s0 r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0/1 0/1 0/1 0/1 0/1 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 8/16-bit access register the stop bit is set only during asynchronous mode. when 7-bit transfer is selected, the bit order is set only to 'lsb first'.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 223 a b c d e f g h i j k l m n o p q r s t u v w x y z sc0trb : x'00fd82' serial 0 transmit/ receive buffer 8-bit access register sc0 sc0 sc0 sc0 sc0 sc0 sc0 sc0 trb7 trb6 trb5 trb4 trb3 trb2 trb1 trb0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 7:0 serial transmit/receive data transmission starts by writing the data into this register. the transmission starts after 1 cycle or 2 cycles of the trasmission clock. in 7-bit transfer, the msb (bit 7) is ignored. writing to sc0trb register must be oper- ated after verifying that the transmission is not in progress. the data is received by reading this register. the data is read when an interrupt occurs or the sc0rxa flag of the sc0str register is 1. in 7-bit transfer, the msb (bit 7) becomes 0.
chapter 9 appendix 224 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g sc0str : x'00fd83' serial 0 status register 8-bit access register (16-bit access is possible from even address) sc0 sc0 sc0 sc0 sc0 sc0 sc0 sc0 tby rby isp rxa ist fe pe oe rrrrrrrr 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 7 transmission busy flag 6 reception busy flag 5i 2 c stop sequence detect 4 received data 3i 2 c start sequence detect 2 framing error 1 parity error 0 overrun error 0: ready to transmit 1: transmission in progress 0: ready to receive 1: reception in progress 0: undetected 1: detected 0: no received data 1: received data 0: undetected 1: detected 0: no error 1: error 0: no error 1: error 0: no error 1: error a framing error occurs when the stop bit is 0. framing error data is updated whenever the stop bit is received. a parity error occurs when the parity bit is 1 although it is set to 0, when the parity bit is 0 al- though it is set to 1, when the parity bit is odd although it is set to even, and when the parity bit is even although it is set to odd. parity error data is updated whenever the parity bit is re- ceived. an overrun error occurs when the next data is received com- pletely before the cpu reads the received data (sc3trb). over- run error data is updated when- ever the last data bit (seventh or eighth bit) is received. do not use the sc3rby flag to set polling for the received data wait in clock synchronous mode. use the interrupt service rou- tine, the serial interrupt flag or the sc3rxa flag.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 225 a b c d e f g h i j k l m n o p q r s t u v w x y z sc1ctr : x'00fd90' serial 1 control register 15 transmit enable 14 receive enable 13 break transmission 12 i 2 c start or stop sequence 11 protocol selection 9 bit order selection 8i 2 c mode selection 7 character length 6:4 parity bit selection 3 stop bit selection 2 open-drain control for i 2 c pin 1:0 serial 1 clock source selection 0: disable 1: enable 0: disable 1: enable 0: don't break 1: break (set sbo to 0) 0: stop sequence output when changing this bit from 1 to 0. 1: start sequence output when changing this bit from 0 to 1. 0: asynchronous mode 1: clock synchronous mode, i 2 c mode 0: lsb first 1: msb first (select only when the character length is 8-bit.) 0: i 2 c mode off 1: i 2 c mode on 0: 7-bit 1: 8-bit 000: none 100: 0 (output low) 101: 1 (output high) 110: even (1s are even) 111: odd (1s are odd) others: reserved 0: 1-bit 1: 2-bit 0: off 1: on 00: sbt1 pin 01: timer 2 underflow/16 10: timer 2 underflow/2 11: timer 3 underflow/16 sc1 sc1 sc1 sc1 sc1 - sc1 sc1 sc1 sc1 sc1 sc1 sc1 sc1 sc1 sc1 ten ren bre i2c ptl od i2cm ln pty2 pty1 pty0 sb pod s1 s0 r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0/1 0/1 0/1 0/1 0/1 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 8/16-bit access register the stop bit is set only during asynchronous mode. when 7-bit transfer is selected, the bit order is set only to 'lsb first'.
chapter 9 appendix 226 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g sc1trb : x'00fd92' serial 1 transmit/ receive buffer 8-bit access register transmission starts by writing the data into this register. the transmission starts after 1 cycle or 2 cycles of the trasmission clock. in 7-bit transfer, the msb (bit 7) is ignored. writing to sc1trb register must be oper- ated after verifying that the transmission is not in progress. the data is received by reading this register. the data is read when an interrupt occurs or the sc1rxa flag of the sc1str register is 1. in 7-bit transfer, the msb (bit 7) becomes 0. sc1 sc1 sc1 sc1 sc1 sc1 sc1 sc1 trb7 trb6 trb5 trb4 trb3 trb2 trb1 trb0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 7:0 serial transmit/receive data
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 227 a b c d e f g h i j k l m n o p q r s t u v w x y z sc1str : x'00fd93' serial 1 status register 8-bit access register (16-bit access is possible from even address) sc1 sc1 sc1 sc1 sc1 sc1 sc1 sc1 tby rby isp rxa ist fe pe oe rrrrrrrr 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 7 transmission busy flag 6 reception busy flag 5i 2 c stop sequence detect 4 received data 3i 2 c start sequence detect 2 framing error 1 parity error 0 overrun error 0: ready to transmit 1: transmission in progress 0: ready to receive 1: reception in progress 0: undetected 1: detected 0: no received data 1: received data 0: undetected 1: detected 0: no error 1: error 0: no error 1: error 0: no error 1: error a framing error occurs when the stop bit is 0. framing error data is updated whenever the stop bit is received. a parity error occurs when the parity bit is 1 although it is set to 0, when the parity bit is 0 al- though it is set to 1, when the parity bit is odd although it is set to even, and when the parity bit is even although it is set to odd. parity error data is updated whenever the parity bit is re- ceived. an overrun error occurs when the next data is received com- pletely before the cpu reads the received data (sc3trb). over- run error data is updated when- ever the last data bit (seventh or eighth bit) is received. do not use the sc3rby flag to set polling for the received data wait in clock synchronous mode. use the interrupt service rou- tine, the serial interrupt flag or the sc3rxa flag.
chapter 9 appendix 228 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g - an an an - an an an an an - - an an an an nch2 nch1 nch0 1ch2 1ch1 1ch0 en tm1 ck1 ck0 md1 md0 r r/w r/w r/w r r/w r/w r/w r/w r/w r r r/w r/w r/w r/w 0000000000000000 0 0/1 0/1 0/1 0 0/1 0/1 0/1 0/1 0/1 0 0 0/1 0/1 0/1 0/1 1514131211109876543210 14:12 channel selection for multiple channel conversion 10:8 channel selection for single channel conversion 7 conversion start/execution flag 6 conversion start at timer 1 underflow 3:2 clock source selection 1:0 operating mode selection 000: convert an0 001: convert from an0 to an1 010: convert from an0 to an2 011: convert from an0 to an3 100: convert from an0 to an4 101: convert from an0 to an5 110: convert from an0 to an6 111: convert from an0 to an7 000: convert an0 001: convert an1 010: convert an2 011: convert an3 100: convert an4 101: convert an5 110: convert an6 111: convert an7 0: reserved 1: conversion start/conversion in progress 0: disable 1: enable 00: sysclk 01: sysclk/2 10: sysclk/4 11: sysclk/8 00: single channel, single conversion 01: multiple channels, single conversion 10: single channel, continuous conversion 11: multiple channels, continuous conversion anctr : x'00ff00' a/d converter control register 8/16-bit access register
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 229 a b c d e f g h i j k l m n o p q r s t u v w x y z an0buf : x'00fda8' 8/16-bit access register an0buf is a read-only buffer. a/d 0 conversion data buffer 7:0 a/d conversion result of ch 0 (an0 pin) an0 an0 an0 an0 an0 an0 an0 an0 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 rrrrrrrr *note *note *note *note *note *note *note *note 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 *note: undefined an1buf : x'00fda9' 8-bit access register (16-bit access is possible from even address) an1buf is a read-only buffer. a/d 1 conversion data buffer 7:0 a/d conversion result of ch 1 (an1 pin) an1 an1 an1 an1 an1 an1 an1 an1 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 rrrrrrrr *note *note *note *note *note *note *note *note 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 *note: undefined an2buf : x'00fdaa' 8/16-bit access register an2buf is a read-only buffer. a/d 2 conversion data buffer 7:0 a/d conversion result of ch 2 (an2 pin) an2 an2 an2 an2 an2 an2 an2 an2 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 rrrrrrrr *note *note *note *note *note *note *note *note 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 *note: undefined
chapter 9 appendix 230 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g an3buf : x'00fdab' a/d 3 conversion data buffer 7:0 a/d conversion result of ch 3 (an3 pin) an3 an3 an3 an3 an3 an3 an3 an3 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 rrrrrrrr *note *note *note *note *note *note *note *note 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 *note: undefined an4buf : x'00fdac' 8/16-bit access register an4buf is a read-only buffer. a/d 4 conversion data buffer 7:0 a/d conversion result of ch 4 (an4 pin) an4 an4 an4 an4 an4 an4 an4 an4 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 rrrrrrrr *note *note *note *note *note *note *note *note 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 *note: undefined an5buf : x'00fdad' a/d 5 conversion data buffer 7:0 a/d conversion result of ch 5 (an5 pin) an5 an5 an5 an5 an5 an5 an5 an5 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 rrrrrrrr *note *note *note *note *note *note *note *note 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 *note: undefined 8-bit access register (16-bit access is possible from even address) an3buf is a read-only buffer. 8-bit access register (16-bit access is possible from even address) an5buf is a read-only buffer.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 231 a b c d e f g h i j k l m n o p q r s t u v w x y z an6buf : x'00fdae' 8/16-bit access register an6buf is a read-only buffer. a/d 6 conversion data buffer 7:0 a/d conversion result of ch 6 (an6 pin) an6 an6 an6 an6 an6 an6 an6 an6 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 rrrrrrrr *note *note *note *note *note *note *note *note 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 *note: undefined an7buf : x'00fdaf' 8-bit access register (16-bit access is possible from even address) an7buf is a read-only buffer. a/d 7 conversion data buffer 7:0 a/d conversion result of ch 7 (an7 pin) an7 an7 an7 an7 an7 an7 an7 an7 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 rrrrrrrr *note *note *note *note *note *note *note *note 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 *note: undefined
chapter 9 appendix 232 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g tm0bc : x'00fe00' 8/16-bit access register tm0bc is a read-only register. timer 0 binary counter 7:0 timer 0 count value tm0 tm0 tm0 tm0 tm0 tm0 tm0 tm0 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrrr 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 tm1bc : x'00fe01' 8-bit access register (16-bit access is possible from even address) tm1bc is a read-only register. timer 1 binary counter 7:0 timer 1 count value tm1 tm1 tm1 tm1 tm1 tm1 tm1 tm1 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrrr 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 tm2bc : x'00fe02' 8/16-bit access register tm2bc is a read-only register. timer 2 binary counter 7:0 timer 2 count value tm2 tm2 tm2 tm2 tm2 tm2 tm2 tm2 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrrr 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 233 a b c d e f g h i j k l m n o p q r s t u v w x y z tm3bc : x'00fe03' timer 3 binary counter 7:0 timer 3 count value tm3 tm3 tm3 tm3 tm3 tm3 tm3 tm3 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrrr 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 tm4bc : x'00fe04' 8/16-bit access register tm4bc is a read-only register. timer 4 binary counter 7:0 timer 4 count value tm4 tm4 tm4 tm4 tm4 tm4 tm4 tm4 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrrr 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 tm5bc : x'00fe05' timer 5 binary counter 7:0 timer 5 count value tm5 tm5 tm5 tm5 tm5 tm5 tm5 tm5 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrrr 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 8-bit access register (16-bit access is possible from even address) tm3bc is a read-only register. 8-bit access register (16-bit access is possible from even address) tm5bc is a read-only register.
chapter 9 appendix 234 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g tm0br : x'00fe10' 8/16-bit access register tm0br is set to 0 after timer 0 starts. see "4-2 8-bit timer setup examples" for details. timer 0 base register tm0 tm0 tm0 tm0 tm0 tm0 tm0 tm0 br7 br6 br5 br4 br3 br2 br1 br0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 tm1br : x'00fe11' 8-bit access register (16-bit access is possible from even address) tm1br is set to 0 after timer 1 starts. see "4-2 8-bit timer setup examples" for details. timer 1 base register 7:0 timer 1 count cycle tm1 tm1 tm1 tm1 tm1 tm1 tm1 tm1 br7 br6 br5 br4 br3 br2 br1 br0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 tm2br : x'00fe12' 8/16-bit access register tm2br is set to 0 after timer 2 starts. see "4-2 8-bit timer setup examples" for details. timer 2 base register 7:0 timer 2 count cycle tm2 tm2 tm2 tm2 tm2 tm2 tm2 tm2 br7 br6 br5 br4 br3 br2 br1 br0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 7:0 timer 0 count cycle set the count cycle (2 to 256). timer 0 counts the set value plus 1. the valid range for tm0br is 0 to 255. set the count cycle (2 to 256). timer 1 counts the set value plus 1. the valid range for tm1br is 0 to 255. set the count cycle (2 to 256). timer 2 counts the set value plus 1. the valid range for tm2br is 0 to 255.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 235 a b c d e f g h i j k l m n o p q r s t u v w x y z tm3br : x'00fe13' timer 3 base register 7:0 timer 3 count cycle tm3 tm3 tm3 tm3 tm3 tm3 tm3 tm3 br7 br6 br5 br4 br3 br2 br1 br0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 tm4br : x'00fe14' 8/16-bit access register tm4br is set to 0 after timer 4 starts. see "4-2 8-bit timer setup examples" for details. timer 4 base register 7:0 timer 4 count cycle tm4 tm4 tm4 tm4 tm4 tm4 tm4 tm4 br7 br6 br5 br4 br3 br2 br1 br0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 tm5br : x'00fe15' timer 5 base register 7:0 timer 5 count cycle tm5 tm5 tm5 tm5 tm5 tm5 tm5 tm5 br7 br6 br5 br4 br3 br2 br1 br0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 76543210 8-bit access register (16-bit access is possible from even address) tm3br is set to 0 after timer 3 starts. see "4-2 8-bit timer setup examples" for details. 8-bit access register (16-bit access is possible from even address) tm5br is set to 0 after timer 5 starts. see "4-2 8-bit timer setup examples" for details. set the count cycle (2 to 256). timer 3 counts the set value plus 1. the valid range for tm3br is 0 to 255. set the count cycle (2 to 256). timer 4 counts the set value plus 1. the valid range for tm4br is 0 to 255. set the count cycle (2 to 256). timer 5 counts the set value plus 1. the valid range for tm4br is 0 to 255.
chapter 9 appendix 236 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g tm0tm0----tm0tm0 en ld s1 s0 r/w r/w r r r r r/w r/w 00000000 0/1 0/1 0 0 0 0 0/1 0/1 76543210 tm0md : x'00fe20' timer 0 mode register 8/16-bit access register 0: disable 1: enable 0: disable 1: load tm0br to tm0bc, reset the 1/2 divisor circuit, fix tmio output to 0. 00: tm0io pin clock (event timer) 01: system clock/128 10: system clock 11: low-speed clock (32 khz)/4 tm1tm1----tm1tm1 en ld s1 s0 r/w r/w r r r r r/w r/w 00000000 0/1 0/1 0 0 0 0 0/1 0/1 76543210 tm1md : x'00fe21' timer 1 mode register 8-bit access register (16-bit access is possible from even address) 0: disable 1: enable 0: disable 1: load tm1br to tm1bc, reset the 1/2 divisor circuit, fix tmio output to 0. 00: tm1io pin clock (event timer) 01: low-speed clock (32 khz)/4 10: timer 0 output clock 11: system clock 7 tm1bc count 6 tm1br setup 1:0 clock source selection 7 tm0bc count 6 tm0br setup 1:0 clock source selection
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 237 a b c d e f g h i j k l m n o p q r s t u v w x y z tm2 tm2 - - - - tm2 tm2 en ld s1 s0 r/wr/wrrrrr/wr/w 00000000 0/10/100000/10/1 76543210 tm2md : x'00fe22' timer 2 mode register 8/16-bit access register 0: disable 1: enable 0: disable 1: load tm2br to tm2bc, reset the 1/2 divisor circuit, fix tmio output to 0. 00: tm2io pin clock (event timer) 01: timer 1 cascade 10: timer 0 output clock 11: system clock tm3 tm3 - - - - tm3 tm3 en ld s1 s0 r/wr/wrrrrr/wr/w 00000000 0/10/100000/10/1 76543210 tm3md : x'00fe23' timer 3 mode register 8-bit access register (16-bit access is possible from even address) 0: disable 1: enable 0: disable 1: load tm3br to tm3bc, reset the 1/2 divisor circuit, fix tmio output to 0. 00: tm3io pin clock (event timer) 01: timer 2 cascade 10: timer 0 output clock 11: system clock 7 tm3bc count 6 tm3br setup 1:0 clock source selection 7 tm2bc count 6 tm2br setup 1:0 clock source selection
chapter 9 appendix 238 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g tm4tm4----tm4tm4 en ld s1 s0 r/w r/w r r r r r/w r/w 00000000 0/1 0/1 0 0 0 0 0/1 0/1 76543210 tm4md : x'00fe24' timer 4 mode register 8/16-bit access register 0: disable 1: enable 0: disable 1: load tm4br to tm4bc, reset the 1/2 divisor circuit, fix tmio output to 0. 00: tm4io pin clock (event timer) 01: timer 3 cascade 10: timer 0 output clock 11: low-speed clock (32 khz)/4 tm5tm5----tm5tm5 en ld s1 s0 r/w r/w r r r r r/w r/w 00000000 0/1 0/1 0 0 0 0 0/1 0/1 76543210 tm5md : x'00fe25' timer 5 mode register 8-bit access register (16-bit access is possible from even address) 0: disable 1: enable 0: disable 1: load tm5br to tm5bc, reset the 1/2 divisor circuit, fix tmio output to 0. 00: tm5io pin clock (event timer) 01: timer 4 cascade 10: timer 0 output clock 11: low-speed clock (32 khz)/4 7 tm5bc count 6 tm5br setup 1:0 clock source selection 7 tm4bc count 6 tm4br setup 1:0 clock source selection
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 239 a b c d e f g h i j k l m n o p q r s t u v w x y z tm6md : x'00fe30' timer 6 mode register tm6 tm6 - - tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 en nld ud1 ud0 tge one md1 md0 eclr lp asel s2 s1 s0 r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0/1 0/1 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 16-bit access register selecting up/down counting mode is ignored when two- phase encoding is slected. 15 tm6bc count 14 tm6bc, t.f.f., rs.f.f. operation 11:10 up/down counter mode selection (ignored when two- phase encoding is selected.) 9 count start external trigger enable 8 counter operating mode select 7:6 tm6ca, tm6cb operating mode selection 5 tm6bc clear when tm6ic is 1 4 tm6bc clear/tm6ca reload 3 tm6ioa pin output 2:0 clock source selection 0: disable 1: enable 0: set tm6bc, t.f.f., rs.f.f. to 0 1: operate tm6bc, t.f.f., rs.f.f. 00: up counter 01: down counter 10: up when tm6ioa pin is high, down when tm6ioa pin is low 11: up when tm6iob pin is high, down when tm6iob pin is low 0: disable 1: enable 0: repeat 1: one-shot counting 00: compare register (single buffer) 01: compare register (double buffer) 10: capture a when tm6ioa pin is high, capture b when tm6ioa pin is low 11: capture a when tm6ioa pin is high, capture b when tm6iob pin is high 0: don't clear 1: clear* when tm6bc=tm6ca while up counting 0: don't clear tm6bc 1: clear tm6bc** when tm6bc=0 while down counting 0: don't reload tm6ca 1: reload tm6ca*** 0: rs.f.f. output (one-phase pwm) 1: t.f.f. output (two-phase pwm) 000: timer 4 output 001: timer 5 output 010: tm6iob pin clock 011: sysclk 100: two-phase encoder (4x) of tm6ioa pin, tm6iob pin 101: two-phase encoder (1x) of tm6ioa pin, tm6iob pin 11*: reserved during repeat counting, hold the tm6en flag state. during one- shot counting, set the tm6en flag to 0 when tm6bc=tm6ca. counting starts on the falling edge of tm6iob pin. clear tm6en when tm6bc matches tm6ca. * clear tm6bc synchronizing externally. ** clear tm6bc when pwm is output. *** when tm6lp is 1 and up- counting is selected, tm6bc is cleared to 0 on the next cycle if tm6bc counts until tm6bc matches tm6ca or x'ffff'. when down counting is se- lected, tm6bc is set to tm6ca on the next cycle regardless of this bit setting if tm6bc be- comes 0.
chapter 9 appendix 240 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 1514131211109876543210 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrrrrrrrrrrr 0000000000000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tm6bc : x'00fe32' timer 6 binary counter tm6bc is a read-only register. 16-bit access register tm6ca : x'00fe34' tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 16-bit access register when capture is selected, tm6ca reads the captured values and a timer 6 capture a interrupt is gen- erated when capture occurs. when compare is selected, set the pwm cycle. when this register matches the timer 6 binary counter, a timer 6 capture a inter- rupt occurs. timer 6 compare/ capture register a 15:0 timer 6 count value 15:0 timer 6 count cycle set the count cycle minus 1. tm6cb : x'00fe38' tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 tm6 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 16-bit access register when capture is selected, tm6cb reads the captured values and a timer 6 capture b interrupt is gen- erated when capture occurs. when compare is selected, set the pwm cycle. when this register matches the timer 6 binary counter, a timer 6 capture b inter- rupt occurs. timer 6 compare/ capture register b 15:0 timer 6 pwm change or interrupt generation
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 241 a b c d e f g h i j k l m n o p q r s t u v w x y z tm7md : x'00fe40' timer 7 mode register tm7 tm7 - - tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 en nld ud1 ud0 tge one md1 md0 eclr lp asel s2 s1 s0 r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0/1 0/1 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 16-bit access register selecting up/down counting mode is ignored when two- phase encoding is slected. 15 tm7bc count 14 tm7bc, t.f.f., rs.f.f. operation 11:10 up/down counter mode selection (ignored when two- phase encoding is selected.) 9 count start external trigger enable 8 counter operating mode select 7:6 tm7ca, tm7cb operating mode selection 5 tm7bc clear when tm6ic is 1 4 tm7bc clear/tm7ca reload 3 tm7ioa pin output 2:0 clock source selection 0: disable 1: enable 0: set tm7bc, t.f.f., rs.f.f. to 0 1: operate tm7bc, t.f.f., rs.f.f. 00: up counter 01: down counter 10: up when tm7ioa pin is high, down when tm7ioa pin is low 11: up when tm7iob pin is high, down when tm7iob pin is low 0: disable 1: enable 0: repeat 1: one-shot counting 00: compare register (single buffer) 01: compare register (double buffer) 10: capture a when tm7ioa pin is high, capture b when tm7ioa pin is low 11: capture a when tm7ioa pin is high, capture b when tm7iob pin is high 0: don't clear 1: clear* when tm7bc=tm7ca while up counting 0: don't clear tm7bc 1: clear tm7bc** when tm7bc=0 while down counting 0: don't reload tm7ca 1: rel oadtm7ca*** 0: rs.f.f. output (one-phase pwm) 1: t.f.f. output (two-phase pwm) 000: timer 4 output 001: timer 5 output 010: tm7iob pin clock 011: sysclk 100: two-phase encoder (4x) of tm7ioa pin, tm7iob pin 101: two-phase encoder (1x) of tm7ioa pin, tm7iob pin 11*: reserved during repeat counting, hold the tm7en flag state. during one- shot counting, set the tm7en flag to 0 when tm7bc=tm7ca. counting starts on the falling edge of tm7iob pin. clear tm7en when tm7bc matches tm7ca. * clear tm7bc synchronizing externally. ** clear tm7bc when pwm is output. *** when tm7lp is 1 and up- counting is selected, tm7bc is cleared to 0 on the next cycle if tm7bc counts until tm7bc matches tm7ca or x'ffff'. when down counting is se- lected, tm7bc is set to tm7ca on the next cycle regardless of this bit setting if tm7bc be- comes 0.
chapter 9 appendix 242 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 1514131211109876543210 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rrrrrrrrrrrrrrrr 0000000000000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tm7bc : x'00fe42' timer 7 binary counter tm7bc is a read-only register. 16-bit access register tm7ca : x'00fe44' tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 16-bit access register when capture is selected, tm7ca reads the captured values and a timer 7 capture a interrupt is gen- erated when capture occurs. when compare is selected, set the pwm cycle. when this register matches the timer 7 binary counter, a timer 7 capture a inter- rupt occurs. timer 7 compare/ capture register a 15:0 timer 7 count value 15:0 timer 7 count cycle set the count cycle minus 1. tm7cb : x'00fe48' tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 tm7 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 16-bit access register when capture is selected, tm7cb reads the captured values and a timer 7 capture b interrupt is gen- erated when capture occurs. when compare is selected, set the pwm cycle. when this register matches the timer 7 binary counter, a timer 7 capture b inter- rupt occurs. timer 7 compare/ capture register b 15:0 timer 7 pwm change or interrupt generation
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 243 a b c d e f g h i j k l m n o p q r s t u v w x y z wbswp : x'00ffa0' 8/16-bit access register word data byte swap register 15:0 word data byte swap data during read operations, the upper 8 bits and the lower 8 bits are swapped. 5 14 13 12 11 10 1 9876543210 p w s b w 5 1 p w s b w 4 1 p w s b w 3 1 p w s b w 2 1 p w s b w 1 1 p w s b w 0 1 p w s b w 9 p w s b w 8 p w s b w 7 p w s b w 6 p w s b w 5 p w s b w 4 p w s b w 3 p w s b w 2 p w s b w 1 p w s b w 0 w / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / r 0000000000000000 p w s b w 7 p w s b w 6 p w s b w 5 p w s b w 4 p w s b w 3 p w s b w 2 p w s b w 1 p w s b w 0 p w s b w 5 1 p w s b w 4 1 p w s b w 3 1 p w s b w 2 1 p w s b w 1 1 - p w s b w 0 1 p w s b w 9 p w s b w 8 pbswpl : x'00ffa2' 8/16-bit access register pointer data byte swap register (lower) 15:0 pointer data byte swap data during read operations, the upper 8 bits are remain and the lower 8 bits of pbswph are read out in the lower 8 bits. 5 14 13 12 11 10 1 9876543210 p w s b p 5 1 p w s b p 4 1 p w s b p 3 1 p w s b p 2 1 p w s b p 1 1 p w s b p 0 1 p w s b p 9 p w s b p 8 p w s b p 7 p w s b p 6 p w s b p 5 p w s b p 4 p w s b p 3 p w s b p 2 p w s b p 1 p w s b p 0 w / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / r 0000000000000000 p w s b p 5 1 p w s b p 4 1 p w s b p 3 1 p w s b p 2 1 p w s b p 1 1 p w s b p 0 1 p w s b p 9 p w s b p 8 p w s b p 3 2 p w s b p 2 2 p w s b p 1 2 p w s b p 0 2 p w s b p 9 1 p w s b p 8 1 p w s b p 7 1 p w s b p 6 1 pbswph : x'00ffa4' 8/16-bit access register pointer data byte swap register (upper) 7:0 pointer data byte swap data during read operations, the lower 8 bits of pbswpl are read out in the upper 8 bits. 5 14 13 12 11 10 1 9876543210 -------- p w s b p 3 2 p w s b p 2 2 p w s b p 1 2 p w s b p 0 2 p w s b p 9 1 p w s b p 8 1 p w s b p 7 1 p w s b p 6 1 -------- w / rw / rw / rw / rw / rw / rw / rw / r -------- 00000000 -------- p w s b p 7 p w s b p 6 p w s b p 5 p w s b p 4 p w s b p 3 p w s b p 2 p w s b p 1 p w s b p 0 lbswpl : x'00ffa6' 8/16-bit access register long-word data byte swap register (lower) 15:0 long-word data byte swap data during read operations, the lower 8 bits of lbswph are read out in the upper 8 bits and the upper 8 bits of lbswph are read out in the lower 8 bits. 5 14 13 12 11 10 1 9876543210 p w s b l 5 1 p w s b l 4 1 p w s b l 3 1 p w s b l 2 1 p w s b l 1 1 p w s b l 0 1 p w s b l 9 p w s b l 8 p w s b l 7 p w s b l 6 p w s b l 5 p w s b l 4 p w s b l 3 p w s b l 2 p w s b l 1 p w s b l 0 w / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / r 0000000000000000 p w s b l 3 2 p w s b l 2 2 p w s b l 1 2 p w s b l 0 2 p w s b l 9 1 p w s b l 8 1 p w s b l 7 1 p w s b l 6 1 p w s b l 1 3 p w s b l 0 3 p w s b l 9 2 p w s b l 8 2 p w s b l 7 2 p w s b l 6 2 p w s b l 5 2 p w s b l 4 2
chapter 9 appendix 244 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g lbswph : x'00ffa8' 8/16-bit access register long-word data byte swap register (upper) 15:0 long-word data byte swap data during read operations, the lower 8 bits of lbswpl are read out in the upper 8 bits and the upper 8 bits of lbswpl are read out in the lower 8 bits. 5 14 13 12 11 10 1 9876543210 p w s b l 1 3 p w s b l 0 3 p w s b l 9 2 p w s b l 8 2 p w s b l 7 2 p w s b l 6 2 p w s b l 5 2 p w s b l 4 2 p w s b l 3 2 p w s b l 2 2 p w s b l 1 2 p w s b l 0 2 p w s b l 9 1 p w s b l 8 1 p w s b l 7 1 p w s b l 6 1 w / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / rw / r 0000000000000000 p w s b l 7 p w s b l 6 p w s b l 5 p w s b l 4 p w s b l 3 p w s b l 2 p w s b l 1 p w s b l 0 p w s b l 5 1 p w s b l 4 1 p w s b l 3 1 p w s b l 2 1 p w s b l 1 1 p w s b l 0 1 p w s b l 9 p w s b l 8
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 245 a b c d e f g h i j k l m n o p q r s t u v w x y z pplu : x'00ffb0' port pullup control register *note sb1p sb0p pa4p pa3p pa2p pa1p pa0p csp rewep p60p ahp amp alp dhp dlp r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1514131211109876543210 16-bit access register always set bit 15 to 0. 14 pullup resistors of serial 1 related pins (sbt1, sbi1, sbo1) 13 pullup resistors of serial 0 related pins (sbt0, sbi0, sbo0) 12 pullup resistor of irq4 (pa4) 11 pullup resistor of irq3 (pa3) 10 pullup resistor of irq2 (pa2) 9 pullup resistor of irq1 (pa1) 8 pullup resistor of irq0 (pa0) 7 pullup resistors of /cs3 to /cs0 6 pullup resistors of external memory related pins (/re, /bstre, /weh, /wel) 5 pullup resistor of wait (p60) 4 pullup resistors of a23 to a16 3 pullup resistors of a15 to a8 2 pullup resistors of a7 to a0 1 pullup resistors of d15 to d8 0 pullup resistors of d7 to d0 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on 0: off 1: on *note: always set 0.
chapter 9 appendix 246 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 76543210 p0 p0 p0 p0 p0 p0 p0 p0 out7 out6 out5 out4 out3 out2 out1 out0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p0out : x'00ffc0' 8/16-bit access register 7:0 port 0 output 76543210 p1 p1 p1 p1 p1 p1 p1 p1 out7 out6 out5 out4 out3 out2 out1 out0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p1out : x'00ffc1' 8-bit access register (16-bit access is possible from even address) 7:0 port 1 output 76543210 p2 p2 p2 p2 p2 p2 p2 p2 out7 out6 out5 out4 out3 out2 out1 out0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p2out : x'00ffc2' 8/16-bit access register 7:0 port 2 output 76543210 p3 p3 p3 p3 p3 p3 p3 p3 out7 out6 out5 out4 out3 out2 out1 out0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p3out : x'00ffc3' 8-bit access register (16-bit access is possible from even address) 7:0 port 3 output port 3 output register port 2 output register port 1 output register port 0 output register
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 247 a b c d e f g h i j k l m n o p q r s t u v w x y z 76543210 p4 p4 p4 p4 p4 p4 p4 p4 out7 out6 out5 out4 out3 out2 out1 out0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p4out : x'00ffc4' 8/16-bit access register 7:0 port 4 output 76543210 p5 p5 p5 p5 p5 p5 p5 p5 out7 out6 out5 out4 out3 out2 out1 out0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p5out : x'00ffc5' 8-bit access register (16-bit access is possible from even address) 7:0 port 5 output 76543210 ----p6p6p6p6 out3 out2 out1 out0 rrrrr/wr/wr/wr/w 00000000 00000/10/10/10/1 p6out : x'00ffc6' 8/16-bit access register 3:0 port 6 output port 4 output register port 5 output register port 6 output register
chapter 9 appendix 248 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 76543210 - - p7 p7 p7 p7 p7 p7 out5 out4 out3 out2 out1 out0 r r r/w r/w r/w r/w r/w r/w 00000000 0 0 0/1 0/1 0/1 0/1 0/1 0/1 p7out : x'00ffc7' 8-bit access register (16-bit access is possible from even address) 5:0 port 7 output port 7 output register 76543210 p8 p8 p8 p8 p8 p8 p8 p8 out7 out6 out5 out4 out3 out2 out1 out0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p8out : x'00ffc8' 8/16-bit access register 7:0 port 8 output 76543210 p9 p9 p9 p9 p9 p9 p9 p9 out7 out6 out5 out4 out3 out2 out1 out0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p9out : x'00ffc9' 8-bit access register (16-bit access is possible from even address) 7:0 port 9 output 76543210 - - pa pa pa pa pa pa out5 out4 out3 out2 out1 out0 r r r/w r/w r/w r/w r/w r/w 00000000 0 0 0/1 0/1 0/1 0/1 0/1 0/1 paout : x'00ffca' 8/16-bit access register 5:0 port a output port 9 output register port 8 output register port a output register
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 249 a b c d e f g h i j k l m n o p q r s t u v w x y z 76543210 p0 p0 p0 p0 p0 p0 p0 p0 in7 in6 in5 in4 in3 in2 in1 in0 rrrrrrrr port port port port port port port port 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p0in : x'00ffd0' 8/16-bit access register 7:0 port 0 input 76543210 p1 p1 p1 p1 p1 p1 p1 p1 in7 in6 in5 in4 in3 in2 in1 in0 rrrrrrrr port port port port port port port port 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p1in : x'00ffd1' 8-bit access register (16-bit access is possible from even address) 7:0 port 1 input 76543210 p2 p2 p2 p2 p2 p2 p2 p2 in7 in6 in5 in4 in3 in2 in1 in0 rrrrrrrr port port port port port port port port 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p2in : x'00ffd2' 8/16-bit access register 7:0 port 2 input port 0 input register port 1 input register port 2 input register
chapter 9 appendix 250 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 76543210 p3 p3 p3 p3 p3 p3 p3 p3 in7 in6 in5 in4 in3 in2 in1 in0 rrrrrrrr port port port port port port port port 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p3in : x'00ffd3' 8-bit access register (16-bit access is possible from even address) 7:0 port 3 input port 3 input register 76543210 p4 p4 p4 p4 p4 p4 p4 p4 in7 in6 in5 in4 in3 in2 in1 in0 rrrrrrrr port port port port port port port port 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p4in : x'00ffd4' 8/16-bit access register 7:0 port 4 input 76543210 p5 p5 p5 p5 p5 p5 p5 p5 in7 in6 in5 in4 in3 in2 in1 in0 rrrrrrrr port port port port port port port port 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p5in : x'00ffd5' 8-bit access register (16-bit access is possible from even address) 7:0 port 5 input port 5 input register port 4 input register
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 251 a b c d e f g h i j k l m n o p q r s t u v w x y z 76543210 ----p6p6p6p6 in3 in2 in1 in0 rrrrrrrr 0000 port port port port 00000/10/10/10/1 p6in : x'00ffd6' 8/16-bit access register 3:0 port 6 input 76543210 - - p7 p7 p7 p7 p7 p7 in5 in4 in3 in2 in1 in0 rrrrrrrr 1 1 port port port port port port 1 1 0/1 0/1 0/1 0/1 0/1 0/1 p7in : x'00ffd7' 8-bit access register (16-bit access is possible from even address) 5:0 port 7 input port 7 input register port 6 input register 76543210 p8 p8 p8 p8 p8 p8 p8 p8 in7 in6 in5 in4 in3 in2 in1 in0 rrrrrrrr port port port port port port port port 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p8in : x'00ffd8' 8/16-bit access register 7:0 port 8 input 76543210 p9 p9 p9 p9 p9 p9 p9 p9 in7 in6 in5 in4 in3 in2 in1 in0 rrrrrrrr port port port port port port port port 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p9in : x'00ffd9' 8-bit access register (16-bit access is possible from even address) 7:0 port 9 input port 9 input register port 8 input register
chapter 9 appendix 252 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 76543210 - nmi pa pa pa pa pa pa in5 in4 in3 in2 in1 in0 rrrrrrrr 0 nmi port port port port port port 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 pain : x'00ffda' 8-bit access register (16-bit access is possible from even address) bit 6 is the level of /nmi pin. 5:0 port a input port a input register 76543210 -------p0 dir0 rrrrrrrr/w 00000000 00000000/1 p0dir : x'00ffe0' 8/16-bit access register setting 1 is allowed only when port 0 is used. 0 all pin input/output of port 0 0: input 1: output 76543210 -------p1 dir0 rrrrrrrr/w 00000000 00000000/1 p1dir : x'00ffe1' 8-bit access register (16-bit access is possible from even address) setting 1 is allowed only when port 1 is used. 0 all pin input/output of port 1 0: input 1: output port 0 input/output control register port 1 input/output control register
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 253 a b c d e f g h i j k l m n o p q r s t u v w x y z 76543210 ---p2---p2 dir4 dir0 r r r r/w r r r r/w 00000000 0 0 0 0/1 0 0 0 0/1 p2dir : x'00ffe2' 8/16-bit access register selecting 1 is not allowed in ad- dress/data separated mode dur- ing processor mode. 4 bits [7:4] input/output of port 2 0 bits [3:0] input/output of port 2 0: input 1: output 0: input 1: output 76543210 p3 p3 p3 p3 p3 p3 p3 p3 dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p3dir : x'00ffe3' 8-bit access register (16-bit access is possible from even address) 7:0 each pin input/output of port 3 0: input 1: output port 2 input/output control register port 3 input/output control register 76543210 p4 p4 p4 p4 p4 p4 p4 p4 dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p4dir : x'00ffe4' 8/16-bit access register 7:0 each pin input/output of port 4 0: input 1: output port 4 input/output control register selecting 1 is not allowed in ad- dress/data separated mode dur- ing processor mode. selecting 1 is not allowed in ad- dress/data separated mode dur- ing processor mode.
chapter 9 appendix 254 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 76543210 p5 p5 p5 p5 p5 p5 p5 p5 dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p5dir : x'00ffe5' 8-bit access register (16-bit access is possible from even address) setting 1 to bits[7:6] and bits[3:0] of this register is not al- lowed during processor mode. 7:0 each pin input/output of port 5 0: input 1: output 76543210 - - - - p6 p6 p6 p6 dir3 dir2 dir1 dir0 rrrrr/wr/wr/wr/w 00000000 00000/10/10/10/1 p6dir : x'00ffe6' 8/16-bit access register 3:0 each pin input/output of port 6 0: input 1: output port 5 input/output control register port 6 input/output control register 76543210 *note *note p7 p7 p7 p7 p7 p7 dir5 dir4 dir3 dir2 dir1 dir0 r r r/w r/w r/w r/w r/w r/w 00000000 0 0 0/1 0/1 0/1 0/1 0/1 0/1 p7dir : x'00ffe7' 8-bit access register (16-bit access is possible from even address) 5:0 each pin input/output of port 7 0: input 1: output port 7 input/output control register setting 1 to bits[3:1] of this regis- ter is not allowed during proces- sor mode. *note: always set 0.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 255 a b c d e f g h i j k l m n o p q r s t u v w x y z 76543210 p8 p8 p8 p8 p8 p8 p8 p8 dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p8dir : x'00ffe8' 8/16-bit access register 7:0 each pin input/output of port 8 0: input 1: output 76543210 p9 p9 p9 p9 p9 p9 p9 p9 dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p9dir : x'00ffe9' 8-bit access register (16-bit access is possible from even address) 7:0 each pin input/output of port 9 0: input 1: output port 8 input/output control register port 9 input/output control register 76543210 - - pa pa pa pa pa pa dir5 dir4 dir3 dir2 dir1 dir0 r r r/w r/w r/w r/w r/w r/w 00000000 0 0 0/1 0/1 0/1 0/1 0/1 0/1 padir : x'00ffea' 8/16-bit access register 5:0 each pin input/output of port a 0: input 1: output port a input/output control register
chapter 9 appendix 256 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 76543210 -------p0 md0 rrrrrrrr/w 00000000 00000000/1 p0md : x'00fff0' 8/16-bit access register p0md is valid and used as a port when /word pin = 'h' and memmdn[8] (n=1 to 3) = 'h'. 0 port 0 output 0: p07 to p00 output 1: d7 to d0 (ad7 to ad0) i/o 76543210 -------p1 md0 rrrrrrrr/w 00000000 00000000/1 p1md : x'00fff1' 8-bit access register (16-bit access is possible from even address) 0 port 1 output 0: p17 to p10 output 1: d15 to d8 (ad15 to ad8) i/o port 0 output mode register port 1 output mode register 76543210 ---p2---p2 md4 md0 r r r r/w r r r r/w 00000000 0 0 0 0/1 0 0 0 0/1 p2md : x'00fff2' 8/16-bit access register 4 port 2 output 0 port 2 output 0: p27 to p24 output 1: a07 to a04 output 0: p23 to p20 output 1: a03 to a00 output port 2 output mode register p2md is invalid in address/data separated mode during proces- sor mode. p1md is invalid during proces- sor mode.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 257 a b c d e f g h i j k l m n o p q r s t u v w x y z 76543210 p3 p3 p3 p3 p3 p3 p3 p3 md7 md6 md5 md4 md3 md2 md1 md0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p3md : x'00fff3' 8-bit access register (16-bit access is possible from even address) 7 port 3 output 6 port 3 output 5 port 3 output 4 port 3 output 3 port 3 output 2 port 3 output 1 port 3 output 0 port 3 output 0: p37 output 1: a15 output 0: p36 output 1: a14 output 0: p35 output 1: a13 output 0: p34 output 1: a12 output 0: p33 output 1: a11 output 0: p32 output 1: a10 output 0: p31 output 1: a09 output 0: p30 output 1: a08 output port 3 output mode register p3md is invalid in address/data separated mode during proces- sor mode. 76543210 p4 p4 p4 p4 p4 p4 p4 p4 md7 md6 md5 md4 md3 md2 md1 md0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p4md : x'00fff4' 8/16-bit access register 7 port 4 output 6 port 4 output 5 port 4 output 4 port 4 output 3 port 4 output 2 port 4 output 1 port 4 output 0 port 4 output 0: p47 output 1: a23 output or wdout output* 0: p46 output 1: a22 output or stop output* 0: p45 output 1: a21 output 0: p44 output 1: a20 output 0: p43 output 1: a19 output 0: p42 output 1: a18 output 0: p41 output 1: a17 output 0: p40 output 1: a16 output port 4 output mode register bits[5:0] of p4md are invalid during processor mode. * selection is determined by set- ting with p6md.
chapter 9 appendix 258 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 76543210 - p5p5p5p5p5p5p5 md6 md5 md4 md3 md2 md1 md0 r r/w r/w r/w r/w r/w r/w r/w 00000000 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p5md : x'00fff5' 8-bit access register (16-bit access is possible from even address) 6 port 5 output 5 port 5 output 4 port 5 output 3 port 5 output 2 port 5 output 1 port 5 output 0 port 5 output 0: p56 output 1: /bstre output (address/data separated mode) 0: p56 output 1: ale (/ale) output (address/data shared mode) 0: p55 output 1: /brack output 0: p54 output 1: /breq input 0: p53 output 1: /cs3 output 0: p52 output 1: /cs2 output 0: p51 output 1: /cs1 output 0: p50 output 1: /cs0 output port 5 output mode register bits[6, 3:0] of p5md are invalid during processor mode. 76543210 p6 p6 - - p6 p6 p6 - md7 md6 md3 md2 md1 r/w r/w r r r/w r/w r/w r 00000000 0/1 0/1 0 0 0/1 0/1 0/1 0 p6md : x'00fff6' 8/16-bit access register 7 selection when p4md7 is high 6 selection when p4md6 is high 3 port 6 output 2 port 6 output 1 port 6 output 0: a23 output 1: wdout output 0: a22 output 1: stop output 0: p63 output 1: /weh output 0: p62 output 1: /wel output 0: p61 output 1: /re output port 6 output mode register bits[3:1] of p6md are invalid during processor mode.
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 259 a b c d e f g h i j k l m n o p q r s t u v w x y z 76543210 - - p7 - p7 p7 - p7 md5 md3 md2 md0 r r r/w r r/w r/w r r/w 00000000 0 0 0/1 0 0/1 0/1 0 0/1 p7md : x'00fff7' 8-bit access register (16-bit access is possible from even address) 5 port 7 output 3 port 7 output 2 port 7 output 0 port 7 output 0: p75 output 1: sbo1 output 0: p73 output 1: sbt1 output 0: p72 output 1: sbo0 output 0: p70 output 1: sbt0 output port 7 output mode register 76543210 p8 p8 p8 p8 p8 p8 p8 p8 md7 md6 md5 md4 md3 md2 md1 md0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p8md : x'00fff8' 8/16-bit access register 7 port 8 output 6 port 8 output 5 port 8 output 4 port 8 output 3 port 8 output 2 port 8 output 1 port 8 output 0 port 8 output 0: p87 output 1: tm6iob output 0: p86 output 1: tm6ioa output 0: p85 output 1: tm5io output 0: p84 output 1: tm4io output 0: p83 output 1: tm3io output 0: p82 output 1: tm2io output 0: p81 output 1: tm1io output 0: p80 output 1: tm0io output port 8 output mode register
chapter 9 appendix 260 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 76543210 -----p9p9- md2 md1 rrrrrr/wr/wr 00000000 000000/10/10 p9md : x'00fff9' 8-bit access register (16-bit access is possible from even address) 2 port 9 output 1 port 9 output 0: p92 output 1: tm7iob output 0: p91 output 1: tm7ioa output port 9 output mode register
chapter 9 appendix mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g 261 a b c d e f g h i j k l m n o p q r s t u v w x y z
262 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-2-2 address map x'00fc00' x'00fc30' x'00fd00' x'00fc50' x'00fc40' x'00fd80' x'00fd90' x'00fda0' x'00fe00' x'00fe10' x'00fe20' x'00fe30' x'00fe40' upper 20bit lower 4bit f9 a b c d e6 7 83 4 51 2 remarks 0 iagr sc0trb sc1trb sc0str sc1str an0buf an1buf an2buf an3buf g7icr (vct=14) g6icr (vct=12) g4icr (vct=8) g3icr (vct=6) g5icr (vct=10) sc0ctr sc1ctr anctr internal control reg. memory register interrupt control registers external memory control register timer 8 channels a/d converter ? =16-bit access =8/16-bit access memmd3 memmd2 memmd1 memmd0 exmctr tm4bc tm5bc tm2bc tm3bc tm0bc tm1bc tm4br tm5br tm4md tm5md tm2br tm3br tm2md tm3md tm0br tm1br tm0md tm1md tm6md tm7md tm6ca tm7ca tm6bc tm7bc tm6cb tm7cb serial interfaces 2 channels ? ? ? ? ? ? ? ? ? ? an4buf an5buf ? an6buf an7buf ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? =8-bit access (16-bit access is possible from an even address.) no symbol = 8-bit access g2icr (vct=4) g1icr (vct=2) g0icr (vct=0) extmd cpum ? memctr ? x'00fd10' x'00fd70' atc registers no access atcctr atcbc see note note: x'00fd72' and x'00fd73' are the system reserved area. accessing those addresses is not allowed. if accessing those are as, the system operation cannot be guaranteed. (1/2)
263 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix x'00ffa0' x'00ffb0' x'00ffe0' x'00ffd0' x'00ffc0' x'00fff0' upper 20bit lower 4bit f9 a b c d e6 7 83 4 51 2 remarks 0 i/o port (2/2) p0out p2out p3out p4out p2in p3in p2dir p3dir p0dir p1dir p3md p0in p1in ? = 16-bit access = 8/16-bit access ? = 8-bit access (16-bit access is possible from an even address.) no symbol = 8-bit access ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p1out ? p5out p6out p7out p8out p9out p4in p5in p6in p7in p8n p9in p4dir p5dir p6dir p7dir p8dir p9dir p4md p5md p6md p7md p8md p9md p2md p0md p1md pb swph wbswp pbswpl lbswpl lbswph pplu ? ? ? ? ? paout pain padir
264 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-2-3 list of pin functions ee = external excitation pin name input level output level schmitt trigger pull-up register reset* 1 reset* 2 reset* 3 breq="l" stop/halt ?p p60,wait ttl cmos yes programmable hi-z hi-z hi-z * * ?q p61,re ttl cmos yes programmable hi-z hi-z hi-z hi-z at re hi-z at re ?r p62,wel ttl cmos yes programmable hi-z hi-z hi-z hi-z at wel hi-z at wel ?s p63,weh ttl cmos yes programmable hi-z hi-z hi-z hi-z at weh hi-z at weh ?t p50,cs0 ttl cmos yes programmable hi-z hi-z hi-z hi-z at cs0 hi-z at cs0 ?u p51,cs1 ttl cmos yes programmable hi-z hi-z hi-z hi-z at cs1 hi-z at cs1 ?v p52,cs2 ttl cmos yes programmable hi-z hi-z hi-z hi-z at cs2 hi-z at cs2 ?w p53,cs3 ttl cmos yes programmable hi-z hi-z hi-z hi-z at cs3 hi-z at cs3 ?x p54,breq ttl cmos yes no hi-z hi-z hi-z low * 10 p55,brack ttl cmos yes no hi-z hi-z hi-z low * 11 p56,ale,ale,bstre ttl cmos yes programmable hi-z hi-z hi-z hi-z except p56 hi-z except p57 12 p57,word ttl cmos yes no hi-z hi-z hi-z * * 13 p20,a00 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a00 hi-z at a00 14 p21,a01 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a01 hi-z at a01 15 p22,a02 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a02 hi-z at a02 16 p23,a03 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a03 hi-z at a03 17vdd - - - - ---- - 18 sysclk - cmos - no high high high * *4 19vss - - - - ---- - 20xi - - - - ---- - 21 xo - - - - high(ee) high(ee) high(ee) * *4 22vdd - - - - ---- - 2 3 osci - - - - ---- - 24 osco - - - - high(ee) high(ee) high(ee) * *5 25 mode cmos - yes no high(input) low(input) low(input) mode mode 26 p24,a04 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a04 hi-z at a04 27 p25,a05 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a05 hi-z at a05 28 p26,a06 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a06 hi-z at a06 29 p27,a07 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a07 hi-z at a07 30 p30,a08 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a08 hi-z at a08 31 p31,a09 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a09 hi-z at a09 32 p32,a10 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a10 hi-z at a10 33 p33,a11 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a11 hi-z at a11 34vdd - - - - ---- - 35 p34,a12 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a12 hi-z at a12 36 p35,a13 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a13 hi-z at a13 37 p36,a14 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a14 hi-z at a14 38 p37,a15 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a15 hi-z at a15 39 p40,a16 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a16 hi-z at a16 40 p41,a17 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a17 hi-z at a17 41 p42,a18 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a18 hi-z at a18 42 p43,a19 ttl cmos yes programmable hi-z hi-z hi-z hi-z at a19 hi-z at a19 43vss - - - - ---- - 44 p44,a20,an4 analog cmos no programmable hi-z hi-z hi-z hi-z at a20 hi-z at a20 45 p45,a21,an5 analog cmos no programmable hi-z hi-z hi-z hi-z at a21 hi-z at a21 46 p46,a22,stop,an6 analog cmos no programmable hi-z hi-z hi-z hi-z at a22 hi-z at a22 47 p47,a23,wdout,an7 analog cmos no programmable hi-z hi-z hi-z hi-z at a23 hi-z at a23 48 p80,tm0io cmos*6 cmos yes no hi-z hi-z hi-z * * 49 p81,tm1io cmos*6 cmos yes no hi-z hi-z hi-z * * 50 p82,tm2io cmos*6 cmos yes no hi-z hi-z hi-z * *
265 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 51 p83,tm3io cmos*6 cmos yes no hi-z hi-z hi-z * * 52 p84,tm4io cmos*6 cmos yes no hi-z hi-z hi-z * * 53 p85,tm5io cmos*6 cmos yes no hi-z hi-z hi-z * * 54vdd - - - - ---- - 55 p86,tm6ioa cmos*6 cmos yes no hi-z hi-z hi-z * * 56 p87,tm6iob cmos*6 cmos yes no hi-z hi-z hi-z * * 57 p90,tm6ic cmos*6 cmos yes no hi-z hi-z hi-z * * 58 p91,tm7ioa cmos*6 cmos yes no hi-z hi-z hi-z * * 59 p92,tm7iob cmos*6 cmos yes no hi-z hi-z hi-z * * 60 p93,tm7ic cmos*6 cmos yes no hi-z hi-z hi-z * * 61vss - - - - ---- - 62 p94,an0 analog cmos no no hi-z hi-z hi-z * * 63 p95,an1 analog cmos no no hi-z hi-z hi-z * * 64 p96,an2 analog cmos no no hi-z hi-z hi-z * * 65 p97,an3 analog cmos no no hi-z hi-z hi-z * * 66 vdd(vpp) - - - - ---- - 67 p70,sbt0 cmos*6 cmos yes programmable hi-z hi-z hi-z * * 68 p71,sbi0 cmos*6 cmos yes programmable hi-z hi-z hi-z * * 69 p72,sbo0 cmos*6 cmos yes programmable hi-z hi-z hi-z * * 70 p73,sbt1 cmos*6 cmos yes programmable hi-z hi-z hi-z * * 71 p74,sbi1 cmos*6 cmos yes programmable hi-z hi-z hi-z * * 72 p75,sbo1 cmos*6 cmos yes programmable hi-z hi-z hi-z * * 73 pull-up - - - - ---- - 74 pull-up - - - - ---- - 75 nmi cmos*6 - yes no nmi nmi nmi nmi nmi 76 pa0,irq0 ttl cmos yes programmable hi-z hi-z hi-z * * 77 pa1,irq1 ttl cmos yes programmable hi-z hi-z hi-z * * 78 pa2,irq2 ttl cmos yes programmable hi-z hi-z hi-z * * 79 pa3,irq3 ttl cmos yes programmable hi-z hi-z hi-z * * 80 pa4,irq4 ttl cmos yes programmable hi-z hi-z hi-z * * 81 pa5,adsep cmos cmos yes no hi-z highinput) low(input) * * 82 rst cmos - yes al ways low(input) low(input) low(input) high high 83vdd - - - - ---- - 84 p00,d00,ad00 ttl cmos no programmable hi-z hi-z hi-z hi-z except p00 hi-z except p00 85 p01,d01,ad01 ttl cmos no programmable hi-z hi-z hi-z hi-z except p01 hi-z except p01 86 p02,d02,ad02 ttl cmos no programmable hi-z hi-z hi-z hi-z except p02 hi-z except p02 87 p03,d03,ad03 ttl cmos no programmable hi-z hi-z hi-z hi-z except p03 hi-z except p03 88 p04,d04,ad04 ttl cmos no programmable hi-z hi-z hi-z hi-z except p04 hi-z except p04 89 p05,d05,ad05 ttl cmos no programmable hi-z hi-z hi-z hi-z except p05 hi-z except p05 90 p06,d06,ad06 ttl cmos no programmable hi-z hi-z hi-z hi-z except p06 hi-z except p06 91 p07,d07,ad07 ttl cmos no programmable hi-z hi-z hi-z hi-z except p07 hi-z except p07 92vss - - - - ---- - 93 p10,d08,ad08 ttl cmos no programmable hi-z hi-z hi-z hi-z except p10 hi-z except p10 94 p11,d09,ad09 ttl cmos no programmable hi-z hi-z hi-z hi-z except p11 hi-z except p11 95 p12,d10,ad10 ttl cmos no programmable hi-z hi-z hi-z hi-z except p12 hi-z except p12 96 p13,d11,ad11 ttl cmos no programmable hi-z hi-z hi-z hi-z except p13 hi-z except p13 97 p14,d12,ad12 ttl cmos no programmable hi-z hi-z hi-z hi-z except p14 hi-z except p14 98 p15,d13,ad13 ttl cmos no programmable hi-z hi-z hi-z hi-z except p15 hi-z except p15 99 p16,d14,ad14 ttl cmos no programmable hi-z hi-z hi-z hi-z except p16 hi-z except p16 100 p17,d15,ad15 ttl cmos no programmable hi-z hi-z hi-z hi-z except p17 hi-z except p17 *: depends on pin setting *1: single-chip mode *2:processor mode (address/data separated mode) y *3: processor mode (address/data shared mode ) *4: high during stop mode *5:high during stop and halt 1 mode *6:ttl in the mn102l490a
mov dm,an dm 266 mn10200 series linear addressing version instructions instruction mnemonic operation vx cx nx zx vf cf nf zf flag op ex. code size cycle machine code mov movx movb mn102l00 series instruction set notes: * 1 it is not possible to specify that dn=dm. * 2 this instruction is supported by the assembler. for "mov (d8,an),am" the assembler will generate a bit pattern for d8=0. * 3 this instruction is supported by the assembler. for "mov am,(d8,an)" the assembler will generate a bit pattern for d8=0. * 4 this instruction is supported by the assembler. the assembler generates bit patterns for the two instructions "movbu (an),dm" and "extxb dm". * 5 this instruction is supported by the assembler. the assembler generates bit patterns for the two instructions "movbu (abs16),d n" and "extxb dn". 9-3 mn10200 series linear addressing version instructions chapter 9 appendix
267 mn10200 series linear addressing version instructions chapter 9 appendix movb dn,(abs16) dn mdr vx cx nx zx vf cf nf zf instruction mnemonic operation flag op ex. code size cycle machine code movb movbu ext extx extxu extxb extxbu add addc addnf sub subc mul mulu divu notes: * 6 32-bit sign extended word data * 7 24-bit sign extended word data * 8 24-bit zero extended word data * 9 24-bit sign extended byte data * 10 24-bit zero extended byte data * 11 addition without changing flag * 12 16 * 13 16 * 14 32?16 = 1616 (unsigned)
268 mn10200 series linear addressing version instructions chapter 9 appendix cmp and or xor not asr lsr ror rol btst bset bclr bcc vx cx nx zx vf cf nf zf instruction mnemonic operation flag cmp dn,dm dm-dn e psw 0 000 psw 0 00 psw 0 000 psw 0 000 * 15 16-bit computation * 16 performed under the conditions of bus lock and disabled interrupts. * 17 src=dest (lower 16 bits) * 18 src * 19 src>dest (lower 16 bits, signed)
chapter 9 appendix bcc bccx vx cx nx zx vf cf nf zf instruction mnemonic operation flag ble label if ((vf^nf)|zf)=1, eeeeeeeee 2 2/1 e3:d8 *20 pc+2+d8(label) * 20 src * 21 src * 22 srcdest (lower 16 bits, unsigned) * 24 src * 25 src * 26 src 270 mn10200 series linear addressing version instructions chapter 9 appendix bltx label if (vx^nx)=1, eeeeeeeee 3 3/2 f5:e0:d8 *33 pc+3+d8(label) * 33 src>dest (24 bits, signed) * 34 src * 35 src * 36 srcdest (24 bits, unsigned) * 38 src * 39 src * 40 src chapter 9 appendix jsr label16 a3-4 271 mn10200 series linear addressing version instructions
chapter 9 appendix 272 mn10200 series linear addressing version instructions mn102l00 series instruction map 01 2 3 45 67 89ab cd ef 0 1 2 3 4 5 6 7 8 9 a b c d e f first byte upper/lower mov dm, (an) movb dm, (an) mov (an), dm movbu (an), dm mov dm, (d8, an) mov am (d8, an) mov (d8, an), dm mov (d8, an), am mov dn, dm (when src=dest, mov imm8, dn) add dn, dm sub dn, dm blt label bgt label bge label ble label bcs label bhi label bcc label bls label movb dn, (abs16) add imm8, dn code extended (2 bytes) nop beq label bne label jmp label16 rts bra label code extended (5 bytes) code extended (3 bytes) code extended (4 bytes) rti jsr label16 extxu dn mov (abs16),dn cmp imm8, dn extxb dn mov dn, (abs16) add imm8, an extx dn movbu (abs16),dn mov imm16, an extxbu dn cmp imm16, an mov imm16, dn two-byte instructions (first byte: f0) 01 2 3 45 67 89ab cd ef 0 1 2 3 4 5 6 7 8 9 a b c d e f second byte upper/lower bset dm, (an) bclr dm, (an) jmp (a1) jsr (a1) jmp (a0) jsr (a0) jmp (a2) jsr (a2) jmp (a3) jsr (a3) movb (di, an), dm movbu (di, an), dm movb dm, (di, an)
chapter 9 appendix 273 mn10200 series linear addressing version instructions two-byte instructions (first byte: f1) 01 2 3 45 67 89ab cd ef 0 1 2 3 4 5 6 7 8 9 a b c d e f second byte upper/lower mov (di, an), am mov (di, an), dm mov am, (di, an) mov dm, (di, an) 01 2 3 45 67 89ab cd ef 0 1 2 3 4 5 6 7 8 9 a b c d e f add dm, an sub dm, an cmp dm, an mov dm, an add an, am sub an, am cmp an, am mov an, am addc dn, dm subc dn, dm two-byte instructions (first byte: f2) second byte upper/lower add an, dm sub an, dm cmp an, dm mov an, dm
chapter 9 appendix 274 mn10200 series linear addressing version instructions 01 2 3 45 67 89ab cd ef 0 1 2 3 4 5 6 7 8 9 a b c d e f and dn, dm or dn, dm xor dn, dm rol dn mul dn, dm mulu dn, dm divu dn, dm cmp dn, dm mov d0, mdr two-byte instructions (first byte: f3) second byte upper/lower ror dn asr dn lsr dn mov d0, psw mov psw, dn ext d0 mov d1, mdr mov d1, psw ext d1 mov d2, mdr mov d2, psw ext d2 mov d3, mdr mov d3, psw ext d3 mov mdr, dn not dn 01 2 3 45 67 89ab cd ef 0 1 2 3 4 5 6 7 8 9 a b c d e f mov dm, (d24, an) mov am, (d24, an) movb dm, (d24, an) movx dm, (d24, an) mov dn, (abs24) mov (d24, an), dm jmp label24 mov (abs24), dn five-byte instructions (first byte: f4) second byte upper/lower mov an, (abs24) add imm24, dn mov imm24, dn movb dn, (abs24) add imm24, an mov imm24, an sub imm24, dn cmp imm24, dn sub imm24, an cmp imm24, an movbu (d24, an), dm movb (d24, an), dm movx (d24, an), dm mov (abs24), an movb (abs24), dn movbu (abs24), dn mov (d24, an), am jsr label24
chapter 9 appendix 275 mn10200 series linear addressing version instructions 01 2 3 45 67 89ab cd ef 0 1 2 3 4 5 6 7 8 9 a b c d e f and imm8, dn movb dm, (d8, an) movb (d8, an), dm movbu (d8, an), dm movx dm, (d8, an) movx (d8, an), dm bltx label bgtx label bgex label blex label bcsx label bhix label bccx label blsx label beqx label bnex label bvc label bvs label three-byte instructions (first byte: f5) second byte upper/lower btst imm8, dn or imm8, dn addnf imm8, an bnc label bns label bvcx label bvsx label bncx label bnsx label 01 2 3 45 67 89ab cd ef 0 1 2 3 4 5 6 7 8 9 a b c d e f and imm16, dn movbu (d16, an), dm and imm16 psw four-byte instructions (first byte: f7) second byte upper/lower btst imm16, dn add imm16, an sub imm16, an add imm16, dn sub imm16, dn or imm16 psw mov an, (abs16) or imm16, dn mov (abs16), an cmp imm16, dn xor imm16, dn movx dm,(d16, an) movx (d16, an), dm mov dm,(d16, an) movb dm,(d16, an) mov am,(d16, an) mov (d16, an), am mov (d16, an), dm movb (d16, an), dm
276 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix ; initialization program init equ * ; memory mode setting for block 0 mov mem0_init,d0 mov d0,(amemmd0) ; handshake mode setting mov memctr_init,d0 mov d0,(amemctr) ; pin setting in memory expansion mode or processor mode mov p01m_init,d0 mov d0,(ap01md) mov p01d_init,d0 mov d0,(ap01dir) mov p23m_init,d0 mov d0,(ap23md) mov p23d_init,d0 mov d0,(ap23dir) mov p45m_init,d0 mov d0,(ap45md) mov p45d_init,d0 mov d0,(ap45dir) mov p6m_init,d0 movb d0,(ap6md) mov p6d_init,d0 movb d0,(ap6dir) ; memory mode setting for block1, block2, block 3 mov mem1_init,d0 mov d0,(amemmd1) mov mem2_init,d0 mov d0,(amemmd2) mov mem3_init,d0 mov d0,(amemmd3) ; burst rom setting mov exmem_init,d0 mov d0,(aexmctr) set the number of wait cycles for block 0 to the memmd0 regis- ter. set bit 10 (hswtioe), bit 9 (nwaitioe) and bit 8 (waitset) of the memctr register to 1, 0 and 0 respectively. set pins. set the exmctr register when the burst rom is used, the ale signal polarity is changed, the pulse width of write enable sig- nal is shortened. set the number of wait cycles for each block to the associated memmdn register. (n=1,2,3) 9-4 initialization program after reset, the initialization program must be located in the cs0 area (x'010000' to x'3fffff). in the initialization program, set the number of wait cycles for block 0 to the memmd0 register. next, set the memctr register. always set bits [8:0] of the memctr register to ?00? the num- ber of wait cycles set in the memmd0 register is valid after setting the memctr register. setting the memmd0 register and the memctr register must follow this step. if this step is not followed, writing to the memctr register cannot be guaranteed. recommend to write x?410?to memctr_init. in the program, the following sym- bols and register addresses are equivalent. (amemctr) = (x?c02? (amemmd0) = (x?c30? (amemmd1) = (x?c32? (amemmd2) = (x?c34? (amemmd3) = (x?c36? (aexmctr) = (x?d00? (ap01md) = (x?ff0? (ap01dir) = (x?fe0? (ap23md) = (x?ff2? (ap23dir) = (x?fe2? (ap45md) = (x?ff4? (ap45dir) = (x?fe4? (ap6md) = (x?ff6? (ap6dir) = (x?fe6?
277 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix ; register initialization mov d0,d0 mov d0,d1 mov d0,d2 mov d0,d3 mov d0,a0 mov d0,a1 mov d0,a2 mov stack_top,a3 ; interrupt enable mov init_psw,d0 mov d0,psw clear register to 0. execute this operation although this step is not always required. set the initial value of the stack pointer. (always set the even address.) when using an interrupt, set the interrupt mode and set the inter- rupt enable flag of psw to 1 af- ter setting the stack.
278 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-5 eprom version 9-5-1 overview the mn102lp25x (x: g, z, a) replaces the MN102L25X (x: g, z, a) mask rom with the eprom which is an electrically erasable/programmable memory. the mn102lp25x is sealed in plastic. once the data is written to the prom, the data cannot be erased. using a dedicated adaptor socket, the program is written with the eprom writer (eprom parallel mode). features ? memory capacity 128 kbytes (64 k 16 bits) ... mn102lp25g, mn102lp25z 32 kbytes (16 k 16 bits) ... mn102lp25a ? programming methods word programming, page programming ? pin 40 pins figure 9-5-1 memory map during eprom parallel mode x'00000' x'00000' x'1ffff' x'07fff' mn102lp25g mn102lp25z mn102lp25a eprom [32 kbytes] eprom [128 kbytes]
279 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-5-2 connecting adaptor socket when the cpu becomes the eprom mode, the mn102lp25x stops and writes the pro- gram to eprom. the following figure shows the connection of the dedicated adaptor socket and eprom. figure 9-5-2 pin configuration of adaptor socket 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v dd pgm nc a15 a14 a13 a12 a11 a10 a9 vss a8 a7 a6 a5 a4 a3 a2 a1 a0 v pp ce i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 vss i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v dd pgm nc nc nc a13 a12 a11 a10 a9 vss a8 a7 a6 a5 a4 a3 a2 a1 a0 v pp ce i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 vss i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 oe when programming with the eprom writer, the mn102lp25x must connect to the writer socket correctly. if the mn102lp25x and the writer socket do not connect cor- rectly, the cpu may damage.
280 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix figure 9-5-3 eprom pin configuration mn102lp25x (top view) 100-pin lqfp 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a15* a14* a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 i/o00 i/o01 i/o02 i/o03 i/o04 i/o05 i/o06 i/o07 i/o08 i/o09 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 vpp oe pgm ce a0 a1 a2 open open open v ss v dd * : connect the mn102lp25a to v ss .
281 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix open i-mbit eprom mn102lp25x pin number pin name pin number pin name 1 vpp 66 vpp 2 ce 4 p63 3 i/o15 100 p17 4 i/o14 99 p16 5 i/o13 98 p15 6 i/o12 97 p14 7 i/o11 96 p13 8 i/o10 95 p12 9 i/o9 94 p11 10 i/o8 93 p10 11, 30 vss 1, 5 - 12, 13,17,19 - 20, 23, 25, 40 - 53, 55 - 65, 67 - 75, 80,82,92 12 i/o7 91 p07 13 i/o6 90 p06 14 i/o5 89 p05 15 i/o4 88 p04 16 i/o3 87 p03 17 i/o2 86 p02 18 i/o1 85 p01 19 i/o0 84 p00 20 oe 2 p61 21 a0 14 p21 22 a1 15 p22 23 a2 16 p23 24 a3 26 p24 25 a4 27 p25 26 a5 28 p26 27 a6 29 p27 28 a7 30 p30 29 a8 31 p31 31 a9 32 p32 32 a10 33 p33 33 a11 35 p34 34 a12 36 p35 35 a13 37 p36 36 a14 38 p37 37 a15 39 p40 38 a16 39 pgm 3 p62 40 vdd 22, 34,54,76 - 79,81,83 vdd,pa0 - pa3,pa5 18, 21,24 sysclk, xo, osco p60,p50 - p57,p20,vdd,vss,xi,osci, mode,p41 - p43,vss,p44 - p47, p80 - p85,p86 - p87,p90 - p93, p94 - p97,p70 - p75, nmi, pa4,rst,vss figure 9-5-4 adaptor socket-mn102lp25x pin connections
282 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix table 9-5-1 operating mode selection 9-5-3 programming operating mode the following table describes the operating modes. /ce /oe / pg m v dd v pp ab0 to ab15 d7 to d0 read l l h v dd v dd address input data output output reserved l h h v dd v dd address input high impedance standby h - - v dd v dd - high impedance word program l h l v dd v pp address input data input page latch hlhv dd v dd address input data input program program hhlv dd v pp - high impedance verify l l h v dd v pp address input data output reserved l l l v dd v pp - high impedance lhhv dd v pp - high impedance hllv dd v pp - high impedance hhhv dd v pp - high impedance
283 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix note: v pp (12.5 v) must be applied after v dd (6 v) and off before v dd voltage. do not allow v pp to exceed 13 v including overshot. do not plug or unplug the device while applying v pp (12.5 v). this affaects the reliabil- ity of the device. when /oe = v il (12.5 v), do not change v pp from v il to 12.5 v or from 12.5 v to v il . word programming the word programming is a mode to write 1-word (16-bit) data at a time. to use this programming mode, set v dd = 6 v, v pp = 12.5 v, and address = 0. the data is written by applying 0.2 ms pulses. after each pulse, read is checked. this step is repeated until the read check is ok. additional pulse is applied when the read check is verified. the width of additional pulses is 0.2 ms times the number of pulses required until the read check is verified. the address increments each time the word data is programmed and then the next word data is programmed. this operation repeats until the last address is programmed. after that, setting v dd = v pp = 5 v and reading all addresses ends programming. dc characteristics v dd = 6 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25 c 5 c parameter symbol condition min typ max unit input leakage current i li i li = 0 v to v dd 2 a v ol i ol = 4 ma 0.45 v v oh i oh = -4 ma 2.4 v v il 0.8 v v ih 2.4 v v dd power supply ( write, verif y) i dd 40.0 ma v pp power supply ( write ) i pp /ce = v il 40.0 ma output voltage input voltage
284 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix ac characteristics v dd = 6 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25 c 5 c parameter symbol condition min typ max unit address setup time t as 2 s /oe enable setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s v dd setup time t vcs 2 s v pp setup time t vps 2 s program pulse width t pw 0.19 0.2 0.21 ms additional program pulse width t opw 0.19 5.25 ms /oe setup time t ces 2 s /oe output delay time t oe 0 150 ns
285 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix figure 9-5-5 word program timing address v ih v il v ih v il v ih v il v ih v il v pp v dd 6 v gnd data v pp v dd ce pgm oe t opw t vcs t vps t ds t as t dh t pw t oe data fixed program verify program valid data output t oes data fixed t ds t dh additional program t ah
286 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix figure 9-5-6 word program flow start vpp=12.5 v,v dd =6.0 v address=0 x=0 x=x+1 apply 0.2 ms write pulse verify apply 0.2x ms write pulse v dd =vpp=*5.0 v read all addresses write end fail x=25 yes no ng ok ng yes no ok address increment (address + 2 = address) last address? *4.75 v v dd =vpp 5.25 v
287 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix note: v pp (12.5 v) must be applied after v dd (6 v) and off before v dd voltage. do not allow v pp to exceed 13 v including overshot. do not plug or unplug the device while applying v pp (12.5 v). this affaects the reliabil- ity of the device. when /oe = v il (12.5 v), do not change v pp from v il to 12.5 v or from 12.5 v to v il . page programming the page programming is a mode to write 2-word (32-bit) data. to use this programming mode, first set v dd = 6 v, v pp = 12.5 v. latch address = 0 and 16-bit data. then set address = 2 and the next 16-bit data. the data is written by applying 0.2 ms pulses. after each pulse, read is checked. this step is repeated until the read check is ok. additional pulse is applied when the read check is verified. the width of additional pulses is 0.2 ms times the number of pulses required until the read check is verified. the address increments each time the 2-word data is programmed and then the next 2- word data is programmed. this operation repeats until the last address is programmed. after that, setting v dd = v pp = 5 v and reading all addresses ends programming. dc characteristics v dd = 6 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25 c 5 c parameter symbol condition min typ max unit input leakage current i li i li = 0 v to v dd 2 a v ol i ol = 4 ma 0.45 v v oh i oh = -4 ma 2.4 v v il 0.8 v v ih 2.4 v v dd power supply ( write, verif y) i dd 40.0 ma v pp power supply ( write ) i pp /ce = v il 40.0 ma output voltage input voltage
288 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix ac characteristics v dd = 6 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25 c 5 c parameter symbol condition min typ max unit address setup time t as 2 s noe enable setup time t oes 2 s data setup time t ds 2 s t ah 0 s t ahl 2 s data hold time t dh 2 s v pp setup time t vps 2 s v dd setup time t vcs 2 s npgm pulse width during initial pro g rammin g t pw 0.19 0.2 0.21 ms npgm pulse width during over pro g rammin g t opw 0.19 5.25 ms noe setup time t ces 2 s noe output delay time t oe 0 150 ns noe pulse width during data latch t lw 1 s npgm setup time t pgms 2 s nce hold time t ceh 2 s noe hold time t oeh 2 s address hold time
289 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix figure 9-5-7 page program timing address a2 - a16 v ih v il v ih v il v ih v il v ih v il v ih v il v ih/ v oh v il/ v ol v pp v dd 6 v v dd a1 data v pp v dd nce npgm noe t oes t vcs t vps t oe t ah t ds t as t dh t pgms t ahl t ceh t ces t oeh t opw t pw t lw data fixed program verify page program page data latch
290 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix start vpp=12.5 v,v dd =6.0 v address=0 x=0 x=x+1 apply 0.2 ms write pulse verify apply 0.2x ms write pulse v dd =vpp=*5.0 v read all addresses write end fail x=25 yes no ng on ng yes no ok latch latch address increment (address + 2 = address) last address? *4.75 v v dd =vpp 5.25 v address increment (address + 2 = address) figure 9-5-7 page program flow
291 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix eprom version precautions some of the electrical characteristics may differ from the mask rom version. the read/write test for all bits cannot be performed due to the nature of the device. therefore, storing the written data cannot be fully guaranteed. recommend to perform a high-temperature test after programming the eprom and before implementing the device. program / verify high temp. test 125 c - 48 h read implement figure 9-5-9 high-temperature test flow
292 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6 flash eeprom version 9-6-1 overview the mn102lf25z replaces the mn102l25z mask rom with the 128- kbyte eeprom which is an electrically erasable/programmable memory. the mn102lf25z has two modes: prom programming mode which uses a dedicated writer (a data-i/o labsite writer) and onboard serial pro- gramming mode which the cpu controls. the 128-kbyte flash memory is divided into two spaces as follows: 1. load program area (1 kbyte: x'80000' - x'803ff') this area stores the load program for serial programming. it is used only in prom programming mode. 2. firm area (127 kbytes: x'80400' - x'9ffff') this area stores the user program. it is programmed only in prom writer mode. the operation is guaranteed with up to 100 programming. figure 9-6-1 memory map for flash eeprom version load program area block1: 1 k block2: 15 k block3: 16 k block4: 32 k block5: 6 k block6: 10 k block7: 8 k block8: 8 k block9: 16 k block10: 15 k block11: 1 k firm area x'80000 x'9ffff
293 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6-2 flash eeprom programming the following figure shows the steps of flash memory programming (erase/write). write '0' to entire memory erase (erase process) user data program erase routine figure 9-6-2 flash eeprom program flow as the above figure shows, programming starts after erasing is completed. the whole erase routine consists of two steps: 1. programming process which writes x'0000' to flash eeprom before the actual erase process occurs 2. erase process which operate the actual erasing 9-6-3 prom programming mode in this mode, the mn102lf25z allows a prom writer to program the flash eeprom. the mn102lf25z uses a dedicated adaptor, which connects to the data-i/o's labsite prom writer. (using the dedicated adaptor selects prom programming mode auto- matically.)
294 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6-4 onboard serial programming mode the serial programming mode is used to program the flash rom in the mn102lf25z that is installed on the board. the following sections describe the mn102lf25z hard- ware, system configuration, protocol for this programming mode. when using ydc dedicated writer, please refer to its user manual. the load program is attached to the serial writer. 9-6-5 hardware used in serial programming mode interface the mn102lf25z incorporates the following functions as i/f for serial programming. one 8-bit serial interface data transmission/reception synchronizing external clock bit order: lsb first maximum clock speed: 10 mhz positive input/output logic two input/output pins sbt, sbd reserved for serial interface i/f block diagram 8-bit serail i/f txd rxc,txc sbd (74pin) sbt (73pin) rxd figure 9-6-3 8-bit serial interface block diagram for serial writer
295 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix memory space of internal flash eeprom serial writer load program area the 1-kbyte area from x'80000' stores the load program for serial writer. in onboard serial programming mode, the erasing/programming in this area is protected. (programming is possible by using the parallel writer.) branch instruction to reset start service routine normally, the reset start address is x'80000', but the program branches into x'80408' with the soft branch instruction in the serial writer loader. in this area, the jmp instruction to the actual reset service routine is stored. branch instruction to interrupt service routine normally, the jump address at interrupt is x'80008', but the program branches into x'80410' with the soft branch instruction in the serial writer loader. in this area, the jmp instruction to the actual interrupt service routine is stored. user program area this area stores the user program. address x'80000' - x'803ff' serial writer load program area reserved area user program area branch instruction to reset service routine branch instruction to interrupt service routine 1 kbyte 8 bytes 8 bytes size area x'80400' - x'80407' x'80408' x'80410' x'80418' - x'9ffff' 127 kbytes 8 bytes figure 9-6-4 flash eeprom memory space
296 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6-6 connecting onboard serial programming mode use ydc serial writer for flash microcontroller. all input/output pins must be set to input at reset release. figure 9-6-5 pin configuration during serial programming pins 73, 74 and 82 connect to the serial writer. v dd and vss connect to the external power sources of 5 v and 0 v respectively. in addition, the level is detected by the writer, v dd and vss must be output to the writer. osci and osco must be set to the self-excited oscillation or external excited oscillation. the input pins with no specifications in the above figure are 'don't care'. fix them to v dd or vss. the output pins with no specifica- tions in the above figure must be open. tm2io,p82 tm1io,p81 tm0io,p80 wdout,p47 stop,p46 p45 p44 vss p43 p42 p41 p40 p37 p36 p35 p34 vdd p33 p32 p31 p30 p27 p26 p25 p24 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 mn102lf25z (top view) 100-pin lqfp p60 p61 p62 p63 p50 p51 p52 p53 p54 p55 p56 p57 p20 p21 p22 p23 vdd sysclk vss xi xo vdd osci osco mode /nmi sbd,p77 sbt,p76 sbo1,p75 sbi1,p74 sbt1,p73 sbo0,p72 sbi0,p71 sbt0,p70 vdd an3,p97 an2,p96 an1,p95 an0,p94 vss tm7ic,p93 tm7iob,p92 tm7ioa,p91 tm6ic,p90 tm6iob,p87 tm6ioa,p86 vdd tm5io,p85 tm4io,p84 tm3io,p83 sbd (to writer) sbt (to writer) / reset (to writer) self-excited or exertnal-excited (4 mhz-20 mhz) pa0,/irq0 pa1,/irq1 pa2,/irq2 pa3,/irq3 pa4,/irq4 pa5 /rst vdd p00 p01 p02 p03 p04 p05 p06 p07 vss p10 p11 p12 p13 p14 p15 p16 p17 pins 73 and 74 must be connected to pullup resistors even though writer is not used.
297 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6-7 system configuration for onboard serial programming system configuration target board serial writer ac adaptor rs232c power source v dd figure 9-6-6 system configuration for onboard serial writer the pc sends the program data to the serial writer through rs-232c. the serial writer programs the flash memory through serial communication between the serial writer and the mn102l25z on the target board. the power is required only when the power source is supplied to the target. pin description v dd : 4.5 v - 5.5 v external power supply v dd (for level detection) : v dd level detection pin for target board /rst : reset sbt : serial interface clock supply sbd : serial interface data supply gnd : ground ? v dd detects the v dd level on the target board using the serial writer. if the v dd level is not satisfied, the serial writer outputs an error message. ? /rst outputs microcontroller reset. ? connect pullup resistors to /rst, sbt and sbd on the target board. the pullup resistor value is 4.7 k ? 10 % to 10 k ? 10 %. ? /rst, sbt and sbd are output from the serial writer through an open collector. figure 9-6-7 target board-serial writer connection target board serial writer gnd sbt sbd /rst chip scl1 sda1 /rst 4.7 k ? - 10 k ? v dd = +5 v pin connection for target board
298 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix mn102lf25z clock on the target board ? use the existing clock on the target board for the clock supply to the mn102lf25z on the target board. because of this, the clock frequency of the mn102lf25z differs de- pending on each user purpose. ? the following table shows the clock frequency for the mn102lf25z during serial programming. the clock frequency for the mn102lf25z is assumed to be 20 mhz if the clock frequency is not specified in the manual. if the clock frequency for the mn102lf25z is different from the clock frequency on the target board, the value should be calculated proportionately depending on the clock frequency of the mn102lf25z. max. clock frequency 20 mhz min. clock frequency 4 mhz table 9-6-1 clock frequency
299 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6-8 onboard serial programming mode setup programming mode setup timing to set serial programming mode, the microcontroller must be in write mode. this section describes the pin setup for the serial writer. figure 9-6-8 timing for onboard serial programming mode sbt sbd sbt sbd t1 t2 a b c timing waveform during serial programming normal timing waveform /rst d /rst t3 v dd v dd
300 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix setup steps 1. supply v dd at timing a. at this point, output /rst = sbd = low. 2. through the serial writer, drive /rst for t2 term from timing b when sbt goes high while the mn102lf25z is on. the mn102lf25z initializes. 3. through the serial writer, drive /rst for t3 term from timing c when sbd goes high while the mn102lf25z is on. this informs that the mn102lf25z is con- nected to the serial writer. 4. during t3 term, the serial writer makes sbd pin to input low level longer enough than the mn102lf25z stabilization wait time. load program reset start sbt pin ==high && sbd pin ==low ? yes execute user program no start serial writer load program wait twait1 sbt pin ==high && sbd pin ==low ? yes no has twait2 passed ? no sbt pin ==high && sbd pin ==high ? yes no yes figure 9-6-9 load program start flow conditions 1. when the load program initializes a reset start, sbd = low and sbt = high. 2. the program waits for twait1. 3. sbd must still be low and sbt high. 4. wait that both sbd and sbt become high during twait2. if any above conditions are not met, the program returns to the user program.
301 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6-9 branch to user program branch to reset service routine serial writer ? yes no start serial writer load program execute user program reset start branch to x'80408' figure 9-6-10 reset service routine flow when the reset starts, the serial writer load program initializes only if sbd is low. the program branches to the user program at address x'80408'. branch to interrupt service routine interrupt start address x'80008' branch to x'80410' execute user interrupt service routine jmp x'80410' instruction (3 bytes/2 cycles) (generate 2-cycle delay) write a branch instruction to x'80410' figure 9-6-11 interrupt service routine flow write only the instruction branching to address x'80410' at the interrupt start address (x'80008').
302 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6-10 serial interface for onboard serial programming features fixed-length serial interface ? character length 8 bits ? transmission bit order lsb ? clock source external clock ? maximum transfer speed 5 mbps ( with a 20-mhz oscillator) ? error detection overrun error ? buffer transmit/receive shared buffer single transmit buffer, double receive buffer data timing sbd sbt lsb msb figure 9-6-12 data transfer timing the 8-bit serial data is transfered with lsb first bit order.
303 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix 9-6-11 prom writer/onboard serial programming start end v dd =5.0 v all"0"program user data program erase figure 9-6-13 programming flow
304 mn102l2503/25a/25d/25z/25g/f25z/490a/62d/62f/62g chapter 9 appendix
mn102l2503/25a/25d/25z/25g/ f25z/490a/62d/62f/62g lsi user's manual may, 2000 1st edition ? matsushita electric industrial co., ltd. ? matsushita electronics corporation issued by matsushita electric industrial co., ltd. matsushita electronics corporation
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